2010/1/21 <[email protected]> > Reviewers: Erik Corry, > > Message: > Simulator not done yet. How do you unit test these? Do you? >
Some of the ARM instructions are tested in test/cctest/test-assembler-arm.cc If you commit tested code that uses the instructions at the same time as you commit the new assembler instructions then I don't personally feel a separate test in test-assembler-arm.cc is strictly necessary. > > Description: > Add vstr and vldr floating point load and store to ARM assembler, > disassembler, > and simulator. > > Please review this at http://codereview.chromium.org/545155 > > SVN Base: http://v8.googlecode.com/svn/branches/bleeding_edge/ > > Affected files: > M src/arm/assembler-arm.h > M src/arm/assembler-arm.cc > M src/arm/disasm-arm.cc > > > Index: src/arm/assembler-arm.h > =================================================================== > --- src/arm/assembler-arm.h (revision 3672) > +++ src/arm/assembler-arm.h (working copy) > @@ -796,6 +796,14 @@ > // However, some simple modifications can allow > // these APIs to support D16 to D31. > > + void vldr(const DwVfpRegister dst, > + const Register base, > + int offset, > + const Condition cond = al); > + void vstr(const Register base, > + int offset, > + const DwVfpRegister src, > + const Condition cond = al); > void vmov(const DwVfpRegister dst, > const Register src1, > const Register src2, > Index: src/arm/assembler-arm.cc > =================================================================== > --- src/arm/assembler-arm.cc (revision 3672) > +++ src/arm/assembler-arm.cc (working copy) > @@ -1371,6 +1371,34 @@ > > > // Support for VFP. > +void Assembler::vldr(const DwVfpRegister dst, > + const Register base, > + int offset, > + const Condition cond) { > + // Ddst = MEM(Rbase + 4*offset). > + // Instruction details available in ARM DDI 0406A, A8-628. > + // cond(31-28) | 1101(27-24)| 1001(23-20) | Rbase(19-16) | > + // Vdst(15-12) | 1011(11-8) | offset > + ASSERT(CpuFeatures::IsEnabled(VFP3)); > + emit(cond | 0xD9*B20 | base.code()*B16 | dst.code()*B12 | > + 0xB*B8 | (offset & 255)); > +} > + > + > +void Assembler::vstr(const Register base, > + int offset, > + const DwVfpRegister src, > + const Condition cond) { > + // MEM(Rbase + 4*offset) = Dsrc. > + // Instruction details available in ARM DDI 0406A, A8-786. > + // cond(31-28) | 1101(27-24)| 1000(23-20) | | Rbase(19-16) | > + // Vsrc(15-12) | 1011(11-8) | offset > + ASSERT(CpuFeatures::IsEnabled(VFP3)); > + emit(cond | 0xD8*B20 | base.code()*B16 | src.code()*B12 | > + 0xB*B8 | (offset & 255)); > +} > + > + > void Assembler::vmov(const DwVfpRegister dst, > const Register src1, > const Register src2, > Index: src/arm/disasm-arm.cc > =================================================================== > --- src/arm/disasm-arm.cc (revision 3672) > +++ src/arm/disasm-arm.cc (working copy) > @@ -998,11 +998,22 @@ > // Decode Type 6 coprocessor instructions. > // Dm = vmov(Rt, Rt2) > // <Rt, Rt2> = vmov(Dm) > +// Ddst = MEM(Rbase + 4*offset). > +// MEM(Rbase + 4*offset) = Dsrc. > void Decoder::DecodeType6CoprocessorIns(Instr* instr) { > ASSERT((instr->TypeField() == 6)); > > if (instr->Bit(23) == 1) { > - Unknown(instr); // Not used by V8. > + if (instr->Bits(24, 21) == 0xC && instr->Bits(11, 8) == 0xB) { > + // Load and store double to memory. > + if (instr->Bit(20) == 1) { > + Format(instr, "vstr'cond 'Dd, ['rn + 4*'off8]"); > + } else { > + Format(instr, "vldr'cond 'Dd, ['rn + 4*'off8]"); > + } > + } else { > + Unknown(instr); // Not used by V8. > + } > } else if (instr->Bit(22) == 1) { > if ((instr->Bits(27, 24) == 0xC) && > (instr->Bit(22) == 1) && > > > > -- > v8-dev mailing list > [email protected] > http://groups.google.com/group/v8-dev > -- v8-dev mailing list [email protected] http://groups.google.com/group/v8-dev
