Reviewers: Benedikt Meurer, ulan, paul.l..., akos.palfi.imgtec,
balazs.kilvady,
Description:
MIPS: Fix missing Float32 case in AssembleArchBoolean.
TEST=/mjsunit/asm/embenchen/box2d
BUG=
Please review this at https://codereview.chromium.org/1234533004/
Base URL: https://chromium.googlesource.com/v8/v8.git@master
Affected files (+34, -12 lines):
M src/compiler/mips/code-generator-mips.cc
M src/compiler/mips64/code-generator-mips64.cc
Index: src/compiler/mips/code-generator-mips.cc
diff --git a/src/compiler/mips/code-generator-mips.cc
b/src/compiler/mips/code-generator-mips.cc
index
4d87f2c2434c331db521d7b71e07db2d80bf6fc0..b2dd7146c78f78931034ce8eb8ea8e88dad57f84
100644
--- a/src/compiler/mips/code-generator-mips.cc
+++ b/src/compiler/mips/code-generator-mips.cc
@@ -263,8 +263,8 @@ Condition FlagsConditionToConditionOvf(FlagsCondition
condition) {
return kNoCondition;
}
-FPUCondition FlagsConditionToConditionCmpD(bool& predicate,
- FlagsCondition condition) {
+FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
+ FlagsCondition condition) {
switch (condition) {
case kEqual:
predicate = true;
@@ -992,22 +992,33 @@ void CodeGenerator::AssembleArchBoolean(Instruction*
instr,
__ Branch(USE_DELAY_SLOT, &done, cc, left, right);
__ li(result, Operand(1)); // In delay slot.
- } else if (instr->arch_opcode() == kMipsCmpD) {
+ } else if (instr->arch_opcode() == kMipsCmpD ||
+ instr->arch_opcode() == kMipsCmpS) {
FPURegister left = i.InputDoubleRegister(0);
FPURegister right = i.InputDoubleRegister(1);
bool predicate;
- FPUCondition cc = FlagsConditionToConditionCmpD(predicate, condition);
+ FPUCondition cc = FlagsConditionToConditionCmpFPU(predicate,
condition);
if (!IsMipsArchVariant(kMips32r6)) {
__ li(result, Operand(1));
- __ c(cc, D, left, right);
+ if (instr->arch_opcode() == kMipsCmpD) {
+ __ c(cc, D, left, right);
+ } else {
+ DCHECK(instr->arch_opcode() == kMipsCmpS);
+ __ c(cc, S, left, right);
+ }
if (predicate) {
__ Movf(result, zero_reg);
} else {
__ Movt(result, zero_reg);
}
} else {
- __ cmp(cc, L, kDoubleCompareReg, left, right);
+ if (instr->arch_opcode() == kMipsCmpD) {
+ __ cmp(cc, L, kDoubleCompareReg, left, right);
+ } else {
+ DCHECK(instr->arch_opcode() == kMipsCmpS);
+ __ cmp(cc, W, kDoubleCompareReg, left, right);
+ }
__ mfc1(at, kDoubleCompareReg);
__ srl(result, at, 31); // Cmp returns all 1s for true.
if (!predicate) // Toggle result for not equal.
Index: src/compiler/mips64/code-generator-mips64.cc
diff --git a/src/compiler/mips64/code-generator-mips64.cc
b/src/compiler/mips64/code-generator-mips64.cc
index
b3f8088e55f1403308399881dce3a64723a8c4c0..a8bcb53b9696856a59f705e5c5b03857c1b9a8c2
100644
--- a/src/compiler/mips64/code-generator-mips64.cc
+++ b/src/compiler/mips64/code-generator-mips64.cc
@@ -264,8 +264,8 @@ Condition FlagsConditionToConditionOvf(FlagsCondition
condition) {
}
-FPUCondition FlagsConditionToConditionCmpD(bool& predicate,
- FlagsCondition condition) {
+FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
+ FlagsCondition condition) {
switch (condition) {
case kEqual:
predicate = true;
@@ -1061,22 +1061,33 @@ void
CodeGenerator::AssembleArchBoolean(Instruction* instr,
cc = FlagsConditionToConditionCmp(condition);
__ Branch(USE_DELAY_SLOT, &done, cc, left, right);
__ li(result, Operand(1)); // In delay slot.
- } else if (instr->arch_opcode() == kMips64CmpD) {
+ } else if (instr->arch_opcode() == kMips64CmpD ||
+ instr->arch_opcode() == kMips64CmpS) {
FPURegister left = i.InputDoubleRegister(0);
FPURegister right = i.InputDoubleRegister(1);
bool predicate;
- FPUCondition cc = FlagsConditionToConditionCmpD(predicate, condition);
+ FPUCondition cc = FlagsConditionToConditionCmpFPU(predicate,
condition);
if (kArchVariant != kMips64r6) {
__ li(result, Operand(1));
- __ c(cc, D, left, right);
+ if (instr->arch_opcode() == kMips64CmpD) {
+ __ c(cc, D, left, right);
+ } else {
+ DCHECK(instr->arch_opcode() == kMips64CmpS);
+ __ c(cc, S, left, right);
+ }
if (predicate) {
__ Movf(result, zero_reg);
} else {
__ Movt(result, zero_reg);
}
} else {
- __ cmp(cc, L, kDoubleCompareReg, left, right);
+ if (instr->arch_opcode() == kMips64CmpD) {
+ __ cmp(cc, L, kDoubleCompareReg, left, right);
+ } else {
+ DCHECK(instr->arch_opcode() == kMips64CmpS);
+ __ cmp(cc, W, kDoubleCompareReg, left, right);
+ }
__ dmfc1(at, kDoubleCompareReg);
__ dsrl32(result, at, 31); // Cmp returns all 1s for true.
if (!predicate) // Toggle result for not equal.
--
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