Reviewers: Benedikt Meurer, Rodolph Perfetta (ARM),
Description:
Version 4.5.103.30 (cherry-pick)
Merged 434a291a0a05015d247c3604c27f88caaa181a51
Make FlushICache NOP for Nvidia Denver 1.0 only
[email protected], [email protected]
BUG=4398
Please review this at https://codereview.chromium.org/1308403010/
Base URL: https://chromium.googlesource.com/v8/[email protected]
Affected files (+8, -3 lines):
M include/v8-version.h
M src/arm/assembler-arm.cc
M src/arm64/assembler-arm64.cc
M src/base/cpu.h
Index: include/v8-version.h
diff --git a/include/v8-version.h b/include/v8-version.h
index
ffb8f8bf93bed3f779a39515373a664cc68b041d..a2dc5b0db6b28313df786d2a2c8a70f9f7afec15
100644
--- a/include/v8-version.h
+++ b/include/v8-version.h
@@ -11,7 +11,7 @@
#define V8_MAJOR_VERSION 4
#define V8_MINOR_VERSION 5
#define V8_BUILD_NUMBER 103
-#define V8_PATCH_LEVEL 29
+#define V8_PATCH_LEVEL 30
// Use 1 for candidates and 0 otherwise.
// (Boolean macro values are not supported by all preprocessors.)
Index: src/arm/assembler-arm.cc
diff --git a/src/arm/assembler-arm.cc b/src/arm/assembler-arm.cc
index
96bdf79facedebfecd39c57e2cda0668f1f7c006..481a3b5ceddebbc5ddc6b9355675c02beba20696
100644
--- a/src/arm/assembler-arm.cc
+++ b/src/arm/assembler-arm.cc
@@ -128,7 +128,8 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
if (FLAG_enable_32dregs && cpu.has_vfp3_d32()) supported_ |= 1u <<
VFP32DREGS;
if (cpu.implementer() == base::CPU::NVIDIA &&
- cpu.variant() == base::CPU::NVIDIA_DENVER) {
+ cpu.variant() == base::CPU::NVIDIA_DENVER &&
+ cpu.part() <= base::CPU::NVIDIA_DENVER_V10) {
supported_ |= 1u << COHERENT_CACHE;
}
#endif
Index: src/arm64/assembler-arm64.cc
diff --git a/src/arm64/assembler-arm64.cc b/src/arm64/assembler-arm64.cc
index
5445fe1a1b19a9bd8f01a4e9afb80a32f8b3493a..f27d3b97b0fb05d5c72b7ae78c39a76704039b70
100644
--- a/src/arm64/assembler-arm64.cc
+++ b/src/arm64/assembler-arm64.cc
@@ -53,7 +53,8 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
// Probe for runtime features
base::CPU cpu;
if (cpu.implementer() == base::CPU::NVIDIA &&
- cpu.variant() == base::CPU::NVIDIA_DENVER) {
+ cpu.variant() == base::CPU::NVIDIA_DENVER &&
+ cpu.part() <= base::CPU::NVIDIA_DENVER_V10) {
supported_ |= 1u << COHERENT_CACHE;
}
}
Index: src/base/cpu.h
diff --git a/src/base/cpu.h b/src/base/cpu.h
index
f6c5a8506a00582d4fe81b230f0598dd5132c6ab..1dc0a91f6501129ca069fe0048bcc6c53dfcb330
100644
--- a/src/base/cpu.h
+++ b/src/base/cpu.h
@@ -59,6 +59,9 @@ class CPU final {
static const int ARM_CORTEX_A12 = 0xc0c;
static const int ARM_CORTEX_A15 = 0xc0f;
+ // Denver-specific part code
+ static const int NVIDIA_DENVER_V10 = 0x002;
+
// PPC-specific part codes
enum {
PPC_POWER5,
--
--
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