Looks like a case of one particular CPU architecture experiencing
surprising slowdowns for some particular instruction or pattern. Depending
on how widespread the situation is, and on availability+cost of
software-side workarounds, it's not immediately clear whether we want to do
anything about it on the V8 side.

To narrow it down further:
- you could inspect the generated machine code (--print-wasm-code should do
the trick) and/or use low-level profiling (such as Linux' perf tool) to
figure out what exactly the trigger is. If the hypothesis is right that
it's some particular pattern, then it should be possible to write a small
standalone C/C++ program that exhibits the same behavior (godbolt.org is
very helpful for crafting exactly the right code for such things).
- if you can't do that work yourself, then you could significantly help
anyone trying to help you by providing a complete example (i.e., complete
program text plus instructions on how to compile/run it, detailed and
specific enough that one can simply copy/paste them to reproduce what
you're seeing).

It might be possible for us to include a small compiler-side change to
avoid some pattern on some hardware -- *if* there is a feasible alternative
(e.g. we obviously can't just replace "< 0" comparisons with "< 1"
comparisons).
It might also be the case that the right fix is a microcode update, or to
buy new hardware, or to hope that real applications won't experience the
same impact as a microbenchmark. Only learning more about the issue will
tell. Escalating this to AMD, once you have a small self-contained example,
definitely makes sense.


On Tue, Apr 7, 2020 at 12:31 PM Immanuel Haffner <haffner.imman...@gmail.com>
wrote:

> And I should add that i don't see that behaviour for i64, float, or double.
>
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