I understand, thank you very much for your answer. On Monday, April 10, 2023 at 7:39:27 PM UTC+8 [email protected] wrote:
> Because riscv32 run simulator on x86 but riscv64 run on x64. > X86 normalize 0x7FF4000000000000 to 0x7FFC000000000000 by default. > > 在2023年4月10日星期一 UTC+8 16:07:13<[email protected]> 写道： > >> I am writing a test about the vfmv_vf instruction as follows: >> >> ~~~~~~~~~ >> diff --git a/test/cctest/test-assembler-riscv64.cc >> b/test/cctest/test-assembler-riscv64.cc >> index b1e018e9a30..29d8d174c80 100644 >> --- a/test/cctest/test-assembler-riscv64.cc >> +++ b/test/cctest/test-assembler-riscv64.cc >> @@ -2817,6 +2817,26 @@ UTEST_RVV_VF_VFMERGE_VF_FORM_WITH_RES(float, >> int32_t, 32, >> ((mask >> i) & 0x1) ? rs1_fval : >> src[i]) >> #undef UTEST_RVV_VF_VFMERGE_VF_FORM_WITH_RES >> >> +TEST(RISCV_UTEST_vfmv_vf_double_nan) { >> + if (!CpuFeatures::IsSupported(RISCV_SIMD)) return; >> + constexpr uint32_t n = 2; >> + CcTest::InitializeVM(); >> + >> + // int64_t rs1_fval = 0x7ff7654321fedcba; >> + int64_t rs1_fval = 0x7FF4000000000000; >> + int64_t dst[n] = {0}; >> + auto fn = [](MacroAssembler& assm) { >> + __ VU.set(t0, VSew::E64, Vlmul::m1); >> + __ fld(ft0, a0, 0); >> + __ vfmv_vf(v1, ft0); >> + __ vs(v1, a1, 0, VSew::E64); >> + }; >> + GenAndRunTest<int64_t, int64_t>((int64_t)&rs1_fval, (int64_t)dst, fn); >> + for (uint32_t i = 0; i < n; i++) { >> + CHECK_EQ(rs1_fval, dst[i]); >> + } >> +} >> + >> // Tests for vector permutation instructions vector slide instructions >> #define UTEST_RVV_VP_VSLIDE_VI_FORM_WITH_RES(instr_name, type, width, >> array, \ >> expect_res) >> \ >> (END) >> ~~~~~~~~~ >> >> This test has two phenomena in riscv32 and riscv64, riscv32 will >> normalize 0x7FF4000000000000 to 0x7FFC000000000000, while riscv64 will not >> change it. >> >> I know that the instruction vfmv_vf should not call the function >> get_fpu_register_double in the simulator, but should call the function >> get_fpu_register_Float64. >> >> But I don't quite understand why the function get_fpu_register_double >> doesn't normalize nan in riscv64? >> >> -- -- v8-dev mailing list [email protected] http://groups.google.com/group/v8-dev --- You received this message because you are subscribed to the Google Groups "v8-dev" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/v8-dev/19c5abcb-5a6b-4df8-b482-e28199da6cebn%40googlegroups.com.
