There is not a lot of (up to date) documentation. A very brief summary:

The new IR's operations (which replace Turbofan's nodes) are defined in
turboshaft/operations.h
<https://source.chromium.org/chromium/chromium/src/+/main:v8/src/compiler/turboshaft/operations.h>
.
The current state of the pipeline is as follows: We run Turbofan's frontend
and then translate to the Turboshaft IR (in turboshaft/graph-builder.cc
<https://source.chromium.org/chromium/chromium/src/+/main:v8/src/compiler/turboshaft/graph-builder.cc>).
Next, the Turboshaft optimization and lowering phases run on the CFG (see
primarily pipeline.cc
<https://source.chromium.org/chromium/chromium/src/+/main:v8/src/compiler/pipeline.cc>
and
the turboshaft/*-phase.h included from there). Eventually, we translate the
CFG back into Turbofan's sea-of-nodes IR (in turboshaft/recreate-schedule.cc
<https://source.chromium.org/chromium/chromium/src/+/main:v8/src/compiler/turboshaft/recreate-schedule.cc>)
to run the backend.

We are currently working on reimplementing the rest of Turbofan's phases to
have a full Turboshaft CFG pipeline eventually, but we plan to ship a first
version of Turboshaft soonish, which still only covers part of the pipeline
and relies on the translation back and forth.

On Tue, Jul 25, 2023 at 11:05 AM Sam Parker-Haynes <[email protected]>
wrote:

> Hi Nico,
>
> A CFG IR sounds good to me :) I've been hesitate to look as I didn't know
> the status, is there any documentation? Is it currently piggybacking off
> turbofan for some functionality? I can't immediately see where/how graph
> nodes are defined.
>
> cheers,
>
> On Tuesday, July 25, 2023 at 9:37:26 AM UTC+1 Nico Hartmann wrote:
>
>> Hi Sam,
>>
>> We are currently migrating Turbofan to a new CFG-based IR (Turboshaft).
>> This could help.
>>
>> Cheers,
>> Nico
>>
>> On Tue, Jul 25, 2023 at 10:23 AM Sam Parker-Haynes <[email protected]>
>> wrote:
>>
>>> Hi,
>>>
>>> I've been wondering how to go about adding general support for
>>> conditional operations in Turbofan, specifically conditional compares for
>>> AArch64. But I now see that Intel APX extensions also support more
>>> conditional instructions, beyond cmov.
>>>
>>> I'm not a huge fan of flag continuations, as it's been too easy for me
>>> to introduce bugs while using them, so is there a safer way to approach
>>> this?
>>>
>>> Machine-level predication would seem to require a CFG in a form that
>>> isn't really available until during/after jump-threading. So a few
>>> questions about jump threading:
>>> - Could predication happen there?
>>> - Why does jump threading run so late, why not before regalloc?
>>>
>>> And, in general, what is the policy on having optimisation passes that
>>> run on machine code?
>>>
>>> Thanks,
>>> Sam
>>>
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>>> .
>>>
>>
>>
>> --
>> Nico Hartmann | Software Engineer | [email protected] | Chrome - V8
>>
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-- 
Nico Hartmann | Software Engineer | [email protected] | Chrome - V8

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