Thanks Vlad. Still LGTM. :) -- Mads
On Thu, Apr 8, 2010 at 5:34 PM, Vladislav Kaznacheev <[email protected]> wrote: > Sure. On ia32 and x64 there is a special branch for handling a pair of > smis (GenericBinaryOpStub::GenerateSmiCode), so a pair of smis never > triggers a transition. On ARM there is a single code path for all > combinations of operand times so a pair of smis can actually be passed > to the method in question. > > Vlad > > On Thu, Apr 8, 2010 at 7:25 PM, Mads Sig Ager <[email protected]> wrote: >> Can you quickly explain why that assert is triggered on ARM and not on >> the other platforms? >> >> Thanks, -- Mads >> >> On Thu, Apr 8, 2010 at 5:17 PM, Vladislav Kaznacheev >> <[email protected]> wrote: >>> That and a change in BinaryOpIC::GetTypeInfo that also have been >>> breaking debug tests. >>> >>> On Thu, Apr 8, 2010 at 7:12 PM, <[email protected]> wrote: >>>> >>>> LGTM, I suppose the only change to the previous submit is the removal of >>>> the >>>> clearing on GC? >>>> >>>> http://codereview.chromium.org/1629008/show >>> >> > -- v8-dev mailing list [email protected] http://groups.google.com/group/v8-dev To unsubscribe, reply using "remove me" as the subject.
