Reviewers: Erik Corry, Description: ARM: Fix disassembly of double registers
Added a few disassembler tests for vadd, vsub, vmul and vdiv. Please review this at http://codereview.chromium.org/2823036/show SVN Base: http://v8.googlecode.com/svn/branches/bleeding_edge/ Affected files: M src/arm/constants-arm.cc M test/cctest/test-disasm-arm.cc Index: src/arm/constants-arm.cc =================================================================== --- src/arm/constants-arm.cc (revision 4985) +++ src/arm/constants-arm.cc (working copy) @@ -85,7 +85,7 @@ const char* VFPRegisters::Name(int reg, bool is_double) { ASSERT((0 <= reg) && (reg < kNumVFPRegisters)); - return names_[reg + is_double ? kNumVFPSingleRegisters : 0]; + return names_[reg + (is_double ? kNumVFPSingleRegisters : 0)]; } Index: test/cctest/test-disasm-arm.cc =================================================================== --- test/cctest/test-disasm-arm.cc (revision 4985) +++ test/cctest/test-disasm-arm.cc (working copy) @@ -408,8 +408,30 @@ if (CpuFeatures::IsSupported(VFP3)) { CpuFeatures::Scope scope(VFP3); + COMPARE(vadd(d0, d1, d2), + "ee310b02 vadd.f64 d0, d1, d2"); + COMPARE(vadd(d3, d4, d5, mi), + "4e343b05 vadd.f64mi d3, d4, d5"); + + COMPARE(vsub(d0, d1, d2), + "ee310b42 vsub.f64 d0, d1, d2"); + COMPARE(vsub(d3, d4, d5, ne), + "1e343b45 vsub.f64ne d3, d4, d5"); + + COMPARE(vmul(d2, d1, d0), + "ee212b00 vmul.f64 d2, d1, d0"); + COMPARE(vmul(d6, d4, d5, cc), + "3e246b05 vmul.f64cc d6, d4, d5"); + + COMPARE(vdiv(d2, d2, d2), + "ee822b02 vdiv.f64 d2, d2, d2"); + COMPARE(vdiv(d6, d7, d7, hi), + "8e876b07 vdiv.f64hi d6, d7, d7"); + COMPARE(vsqrt(d0, d0), "eeb10bc0 vsqrt.f64 d0, d0"); + COMPARE(vsqrt(d2, d3, ne), + "1eb12bc3 vsqrt.f64ne d2, d3"); } VERIFY_RUN(); -- v8-dev mailing list [email protected] http://groups.google.com/group/v8-dev
