Revision: 5127
Author: [email protected]
Date: Fri Jul 23 04:55:03 2010
Log: Fix aliasing problem in inlined stores on x64 and ia32. The receiver
and the value can share a register. We need to remove this aliasing
before modifying the registers.
I haven't managed to generate a stand-alon test case for this
yet. I'll do that as a separate change. This was found while loading
Wave.
Review URL: http://codereview.chromium.org/3039025
http://code.google.com/p/v8/source/detail?r=5127
Modified:
/branches/bleeding_edge/src/ia32/codegen-ia32.cc
/branches/bleeding_edge/src/x64/codegen-x64.cc
=======================================
--- /branches/bleeding_edge/src/ia32/codegen-ia32.cc Fri Jul 23 04:20:59
2010
+++ /branches/bleeding_edge/src/ia32/codegen-ia32.cc Fri Jul 23 04:55:03
2010
@@ -8968,15 +8968,20 @@
// Allocate scratch register for write barrier.
Result scratch = allocator()->Allocate();
- ASSERT(scratch.is_valid() &&
- result.is_valid() &&
- receiver.is_valid() &&
- value.is_valid());
+ ASSERT(scratch.is_valid());
// The write barrier clobbers all input registers, so spill the
// receiver and the value.
frame_->Spill(receiver.reg());
frame_->Spill(value.reg());
+
+ // If the receiver and the value share a register allocate a new
+ // register for the receiver.
+ if (receiver.reg().is(value.reg())) {
+ receiver = allocator()->Allocate();
+ ASSERT(receiver.is_valid());
+ __ mov(receiver.reg(), Operand(value.reg()));
+ }
// Update the write barrier. To save instructions in the inlined
// version we do not filter smis.
=======================================
--- /branches/bleeding_edge/src/x64/codegen-x64.cc Fri Jul 23 04:20:59 2010
+++ /branches/bleeding_edge/src/x64/codegen-x64.cc Fri Jul 23 04:55:03 2010
@@ -8103,15 +8103,20 @@
// Allocate scratch register for write barrier.
Result scratch = allocator()->Allocate();
- ASSERT(scratch.is_valid() &&
- result.is_valid() &&
- receiver.is_valid() &&
- value.is_valid());
+ ASSERT(scratch.is_valid());
// The write barrier clobbers all input registers, so spill the
// receiver and the value.
frame_->Spill(receiver.reg());
frame_->Spill(value.reg());
+
+ // If the receiver and the value share a register allocate a new
+ // register for the receiver.
+ if (receiver.reg().is(value.reg())) {
+ receiver = allocator()->Allocate();
+ ASSERT(receiver.is_valid());
+ __ movq(receiver.reg(), value.reg());
+ }
// Update the write barrier. To save instructions in the inlined
// version we do not filter smis.
--
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