Revision: 5967
Author: [email protected]
Date: Fri Dec 10 06:10:54 2010
Log: ARM: Fix heap number allocation in lithium-codegen-arm that assumed
that ip can be used as a scratch register. This is not true because
ip is already used for something else in AllocateInNewSpace in the
macro assembler.
Explicitly allocate a temp register for use in the heap number
allocation instead.
Review URL: http://codereview.chromium.org/5788001
http://code.google.com/p/v8/source/detail?r=5967
Modified:
/branches/bleeding_edge/src/arm/lithium-arm.cc
/branches/bleeding_edge/src/arm/lithium-arm.h
/branches/bleeding_edge/src/arm/lithium-codegen-arm.cc
/branches/bleeding_edge/src/arm/macro-assembler-arm.cc
=======================================
--- /branches/bleeding_edge/src/arm/lithium-arm.cc Wed Dec 8 07:03:08 2010
+++ /branches/bleeding_edge/src/arm/lithium-arm.cc Fri Dec 10 06:10:54 2010
@@ -1691,11 +1691,13 @@
} else if (from.IsDouble()) {
if (to.IsTagged()) {
LOperand* value = UseRegister(instr->value());
- LOperand* temp = TempRegister();
-
- // Make sure that temp and result_temp are different registers.
+ LOperand* temp1 = TempRegister();
+ LOperand* temp2 = TempRegister();
+
+ // Make sure that the temp and result_temp registers are
+ // different.
LUnallocated* result_temp = TempRegister();
- LInstruction* result = new LNumberTagD(value, temp);
+ LInstruction* result = new LNumberTagD(value, temp1, temp2);
Define(result, result_temp);
return AssignPointerMap(result);
} else {
=======================================
--- /branches/bleeding_edge/src/arm/lithium-arm.h Tue Dec 7 06:51:49 2010
+++ /branches/bleeding_edge/src/arm/lithium-arm.h Fri Dec 10 06:10:54 2010
@@ -1395,15 +1395,17 @@
class LNumberTagD: public LUnaryOperation {
public:
- explicit LNumberTagD(LOperand* value, LOperand* temp)
- : LUnaryOperation(value), temp_(temp) { }
+ LNumberTagD(LOperand* value, LOperand* temp1, LOperand* temp2)
+ : LUnaryOperation(value), temp1_(temp1), temp2_(temp2) { }
DECLARE_CONCRETE_INSTRUCTION(NumberTagD, "number-tag-d")
- LOperand* temp() const { return temp_; }
+ LOperand* temp1() const { return temp1_; }
+ LOperand* temp2() const { return temp2_; }
private:
- LOperand* temp_;
+ LOperand* temp1_;
+ LOperand* temp2_;
};
=======================================
--- /branches/bleeding_edge/src/arm/lithium-codegen-arm.cc Fri Dec 10
04:12:06 2010
+++ /branches/bleeding_edge/src/arm/lithium-codegen-arm.cc Fri Dec 10
06:10:54 2010
@@ -1733,13 +1733,14 @@
DoubleRegister input_reg = ToDoubleRegister(instr->input());
Register reg = ToRegister(instr->result());
- Register tmp = ToRegister(instr->temp());
+ Register temp1 = ToRegister(instr->temp1());
+ Register temp2 = ToRegister(instr->temp2());
Register scratch = r9;
DeferredNumberTagD* deferred = new DeferredNumberTagD(this, instr);
if (FLAG_inline_new) {
__ LoadRoot(scratch, Heap::kHeapNumberMapRootIndex);
- __ AllocateHeapNumber(reg, tmp, ip, scratch, deferred->entry());
+ __ AllocateHeapNumber(reg, temp1, temp2, scratch, deferred->entry());
} else {
__ jmp(deferred->entry());
}
=======================================
--- /branches/bleeding_edge/src/arm/macro-assembler-arm.cc Tue Dec 7
03:31:57 2010
+++ /branches/bleeding_edge/src/arm/macro-assembler-arm.cc Fri Dec 10
06:10:54 2010
@@ -1060,9 +1060,14 @@
return;
}
+ // Assert that the register arguments are different and that none of
+ // them are ip. ip is used explicitly in the code generated below.
ASSERT(!result.is(scratch1));
ASSERT(!result.is(scratch2));
ASSERT(!scratch1.is(scratch2));
+ ASSERT(!result.is(ip));
+ ASSERT(!scratch1.is(ip));
+ ASSERT(!scratch2.is(ip));
// Check relative positions of allocation top and limit addresses.
// The values must be adjacent in memory to allow the use of LDM.
--
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