Revision: 7908
Author: [email protected]
Date: Tue May 17 03:34:02 2011
Log: MIPS: Remove peeophole optimizations from assembler.
Following r7854.
BUG=
TEST=
Review URL: http://codereview.chromium.org//7037004
http://code.google.com/p/v8/source/detail?r=7908
Modified:
/branches/bleeding_edge/src/mips/assembler-mips.cc
/branches/bleeding_edge/src/mips/assembler-mips.h
=======================================
--- /branches/bleeding_edge/src/mips/assembler-mips.cc Mon May 9 07:28:09
2011
+++ /branches/bleeding_edge/src/mips/assembler-mips.cc Tue May 17 03:34:02
2011
@@ -240,9 +240,7 @@
Assembler::Assembler(Isolate* arg_isolate, void* buffer, int buffer_size)
: AssemblerBase(arg_isolate),
positions_recorder_(this),
- allow_peephole_optimization_(false),
emit_debug_code_(FLAG_debug_code) {
- allow_peephole_optimization_ = FLAG_peephole_optimization;
if (buffer == NULL) {
// Do our own buffer management.
if (buffer_size <= kMinimalBufferSize) {
@@ -279,6 +277,7 @@
trampoline_pool_blocked_nesting_ = 0;
next_buffer_check_ = kMaxBranchOffset - kTrampolineSize;
internal_trampoline_exception_ = false;
+ last_bound_pos_ = 0;
ast_id_for_reloc_info_ = kNoASTId;
}
@@ -1089,158 +1088,6 @@
void Assembler::addiu(Register rd, Register rs, int32_t j) {
GenInstrImmediate(ADDIU, rs, rd, j);
-
- // Eliminate pattern: push(r), pop().
- // addiu(sp, sp, Operand(-kPointerSize));
- // sw(src, MemOperand(sp, 0);
- // addiu(sp, sp, Operand(kPointerSize));
- // Both instructions can be eliminated.
- if (can_peephole_optimize(3) &&
- // Pattern.
- instr_at(pc_ - 1 * kInstrSize) == kPopInstruction &&
- (instr_at(pc_ - 2 * kInstrSize) & ~kRtMask) == kPushRegPattern &&
- (instr_at(pc_ - 3 * kInstrSize)) == kPushInstruction) {
- pc_ -= 3 * kInstrSize;
- if (FLAG_print_peephole_optimization) {
- PrintF("%x push(reg)/pop() eliminated\n", pc_offset());
- }
- }
-
- // Eliminate pattern: push(ry), pop(rx).
- // addiu(sp, sp, -kPointerSize)
- // sw(ry, MemOperand(sp, 0)
- // lw(rx, MemOperand(sp, 0)
- // addiu(sp, sp, kPointerSize);
- // Both instructions can be eliminated if ry = rx.
- // If ry != rx, a register copy from ry to rx is inserted
- // after eliminating the push and the pop instructions.
- if (can_peephole_optimize(4)) {
- Instr pre_push_sp_set = instr_at(pc_ - 4 * kInstrSize);
- Instr push_instr = instr_at(pc_ - 3 * kInstrSize);
- Instr pop_instr = instr_at(pc_ - 2 * kInstrSize);
- Instr post_pop_sp_set = instr_at(pc_ - 1 * kInstrSize);
-
- if (IsPush(push_instr) &&
- IsPop(pop_instr) && pre_push_sp_set == kPushInstruction &&
- post_pop_sp_set == kPopInstruction) {
- if ((pop_instr & kRtMask) != (push_instr & kRtMask)) {
- // For consecutive push and pop on different registers,
- // we delete both the push & pop and insert a register move.
- // push ry, pop rx --> mov rx, ry.
- Register reg_pushed, reg_popped;
- reg_pushed = GetRtReg(push_instr);
- reg_popped = GetRtReg(pop_instr);
- pc_ -= 4 * kInstrSize;
- // Insert a mov instruction, which is better than a pair of push &
pop.
- or_(reg_popped, reg_pushed, zero_reg);
- if (FLAG_print_peephole_optimization) {
- PrintF("%x push/pop (diff reg) replaced by a reg move\n",
- pc_offset());
- }
- } else {
- // For consecutive push and pop on the same register,
- // both the push and the pop can be deleted.
- pc_ -= 4 * kInstrSize;
- if (FLAG_print_peephole_optimization) {
- PrintF("%x push/pop (same reg) eliminated\n", pc_offset());
- }
- }
- }
- }
-
- if (can_peephole_optimize(5)) {
- Instr pre_push_sp_set = instr_at(pc_ - 5 * kInstrSize);
- Instr mem_write_instr = instr_at(pc_ - 4 * kInstrSize);
- Instr lw_instr = instr_at(pc_ - 3 * kInstrSize);
- Instr mem_read_instr = instr_at(pc_ - 2 * kInstrSize);
- Instr post_pop_sp_set = instr_at(pc_ - 1 * kInstrSize);
-
- if (IsPush(mem_write_instr) &&
- pre_push_sp_set == kPushInstruction &&
- IsPop(mem_read_instr) &&
- post_pop_sp_set == kPopInstruction) {
- if ((IsLwRegFpOffset(lw_instr) ||
- IsLwRegFpNegOffset(lw_instr))) {
- if ((mem_write_instr & kRtMask) ==
- (mem_read_instr & kRtMask)) {
- // Pattern: push & pop from/to same register,
- // with a fp + offset lw in between.
- //
- // The following:
- // addiu sp, sp, -4
- // sw rx, [sp, #0]!
- // lw rz, [fp, #-24]
- // lw rx, [sp, 0],
- // addiu sp, sp, 4
- //
- // Becomes:
- // if(rx == rz)
- // delete all
- // else
- // lw rz, [fp, #-24]
-
- if ((mem_write_instr & kRtMask) == (lw_instr & kRtMask)) {
- pc_ -= 5 * kInstrSize;
- } else {
- pc_ -= 5 * kInstrSize;
- // Reinsert back the lw rz.
- emit(lw_instr);
- }
- if (FLAG_print_peephole_optimization) {
- PrintF("%x push/pop -dead ldr fp + offset in middle\n",
- pc_offset());
- }
- } else {
- // Pattern: push & pop from/to different registers
- // with a fp + offset lw in between.
- //
- // The following:
- // addiu sp, sp ,-4
- // sw rx, [sp, 0]
- // lw rz, [fp, #-24]
- // lw ry, [sp, 0]
- // addiu sp, sp, 4
- //
- // Becomes:
- // if(ry == rz)
- // mov ry, rx;
- // else if(rx != rz)
- // lw rz, [fp, #-24]
- // mov ry, rx
- // else if((ry != rz) || (rx == rz)) becomes:
- // mov ry, rx
- // lw rz, [fp, #-24]
-
- Register reg_pushed, reg_popped;
- if ((mem_read_instr & kRtMask) == (lw_instr & kRtMask)) {
- reg_pushed = GetRtReg(mem_write_instr);
- reg_popped = GetRtReg(mem_read_instr);
- pc_ -= 5 * kInstrSize;
- or_(reg_popped, reg_pushed, zero_reg); // Move instruction.
- } else if ((mem_write_instr & kRtMask)
- != (lw_instr & kRtMask)) {
- reg_pushed = GetRtReg(mem_write_instr);
- reg_popped = GetRtReg(mem_read_instr);
- pc_ -= 5 * kInstrSize;
- emit(lw_instr);
- or_(reg_popped, reg_pushed, zero_reg); // Move instruction.
- } else if (((mem_read_instr & kRtMask)
- != (lw_instr & kRtMask)) ||
- ((mem_write_instr & kRtMask)
- == (lw_instr & kRtMask)) ) {
- reg_pushed = GetRtReg(mem_write_instr);
- reg_popped = GetRtReg(mem_read_instr);
- pc_ -= 5 * kInstrSize;
- or_(reg_popped, reg_pushed, zero_reg); // Move instruction.
- emit(lw_instr);
- }
- if (FLAG_print_peephole_optimization) {
- PrintF("%x push/pop (ldr fp+off in middle)\n", pc_offset());
- }
- }
- }
- }
- }
}
@@ -1428,54 +1275,6 @@
LoadRegPlusOffsetToAt(rs);
GenInstrImmediate(LW, at, rd, 0); // Equiv to lw(rd, MemOperand(at,
0));
}
-
- if (can_peephole_optimize(2)) {
- Instr sw_instr = instr_at(pc_ - 2 * kInstrSize);
- Instr lw_instr = instr_at(pc_ - 1 * kInstrSize);
-
- if ((IsSwRegFpOffset(sw_instr) &&
- IsLwRegFpOffset(lw_instr)) ||
- (IsSwRegFpNegOffset(sw_instr) &&
- IsLwRegFpNegOffset(lw_instr))) {
- if ((lw_instr & kLwSwInstrArgumentMask) ==
- (sw_instr & kLwSwInstrArgumentMask)) {
- // Pattern: Lw/sw same fp+offset, same register.
- //
- // The following:
- // sw rx, [fp, #-12]
- // lw rx, [fp, #-12]
- //
- // Becomes:
- // sw rx, [fp, #-12]
-
- pc_ -= 1 * kInstrSize;
- if (FLAG_print_peephole_optimization) {
- PrintF("%x sw/lw (fp + same offset), same reg\n", pc_offset());
- }
- } else if ((lw_instr & kLwSwOffsetMask) ==
- (sw_instr & kLwSwOffsetMask)) {
- // Pattern: Lw/sw same fp+offset, different register.
- //
- // The following:
- // sw rx, [fp, #-12]
- // lw ry, [fp, #-12]
- //
- // Becomes:
- // sw rx, [fp, #-12]
- // mov ry, rx
-
- Register reg_stored, reg_loaded;
- reg_stored = GetRtReg(sw_instr);
- reg_loaded = GetRtReg(lw_instr);
- pc_ -= 1 * kInstrSize;
- // Insert a mov instruction, which is better than lw.
- or_(reg_loaded, reg_stored, zero_reg); // Move instruction.
- if (FLAG_print_peephole_optimization) {
- PrintF("%x sw/lw (fp + same offset), diff reg \n", pc_offset());
- }
- }
- }
- }
}
@@ -1516,23 +1315,6 @@
LoadRegPlusOffsetToAt(rs);
GenInstrImmediate(SW, at, rd, 0); // Equiv to sw(rd, MemOperand(at,
0));
}
-
- // Eliminate pattern: pop(), push(r).
- // addiu sp, sp, Operand(kPointerSize);
- // addiu sp, sp, Operand(-kPointerSize);
- // -> sw r, MemOpernad(sp, 0);
- if (can_peephole_optimize(3) &&
- // Pattern.
- instr_at(pc_ - 1 * kInstrSize) ==
- (kPushRegPattern | (rd.code() << kRtShift)) &&
- instr_at(pc_ - 2 * kInstrSize) == kPushInstruction &&
- instr_at(pc_ - 3 * kInstrSize) == kPopInstruction) {
- pc_ -= 3 * kInstrSize;
- GenInstrImmediate(SW, rs.rm(), rd, rs.offset_);
- if (FLAG_print_peephole_optimization) {
- PrintF("%x pop()/push(reg) eliminated\n", pc_offset());
- }
- }
}
=======================================
--- /branches/bleeding_edge/src/mips/assembler-mips.h Mon May 9 07:28:09
2011
+++ /branches/bleeding_edge/src/mips/assembler-mips.h Tue May 17 03:34:02
2011
@@ -815,12 +815,6 @@
int32_t pc_offset() const { return pc_ - buffer_; }
PositionsRecorder* positions_recorder() { return &positions_recorder_; }
-
- bool can_peephole_optimize(int instructions) {
- if (!allow_peephole_optimization_) return false;
- if (last_bound_pos_ > pc_offset() - instructions * kInstrSize) return
false;
- return reloc_info_writer.last_pc() <= pc_ - instructions * kInstrSize;
- }
// Postpone the generation of the trampoline pool for the specified
number of
// instructions.
@@ -1126,7 +1120,6 @@
friend class BlockTrampolinePoolScope;
PositionsRecorder positions_recorder_;
- bool allow_peephole_optimization_;
bool emit_debug_code_;
friend class PositionsRecorder;
friend class EnsureSpace;
--
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