Reviewers: Mads Ager, Description: ARM: Add PostIndex support to Ldrd/Strd macro fallback code.
BUG=none TEST=none Please review this at http://codereview.chromium.org/7080052/ SVN Base: http://v8.googlecode.com/svn/branches/bleeding_edge/ Affected files: M src/arm/assembler-arm.h M src/arm/macro-assembler-arm.cc Index: src/arm/assembler-arm.h =================================================================== --- src/arm/assembler-arm.h (revision 8139) +++ src/arm/assembler-arm.h (working copy) @@ -451,6 +451,7 @@ Register rn() const { return rn_; } Register rm() const { return rm_; } + AddrMode am() const { return am_; } bool OffsetIsUint12Encodable() const { return offset_ >= 0 ? is_uint12(offset_) : is_uint12(-offset_); Index: src/arm/macro-assembler-arm.cc =================================================================== --- src/arm/macro-assembler-arm.cc (revision 8139) +++ src/arm/macro-assembler-arm.cc (working copy) @@ -654,19 +654,34 @@ ASSERT_EQ(0, dst1.code() % 2); ASSERT_EQ(dst1.code() + 1, dst2.code()); + // V8 does not use this addressing mode, so the fallback code + // below doesn't support it yet. + ASSERT((src.am() != PreIndex) && (src.am() != NegPreIndex)); + // Generate two ldr instructions if ldrd is not available. if (CpuFeatures::IsSupported(ARMv7)) { CpuFeatures::Scope scope(ARMv7); ldrd(dst1, dst2, src, cond); } else { MemOperand src2(src); - src2.set_offset(src2.offset() + 4); - if (dst1.is(src.rn())) { - ldr(dst2, src2, cond); - ldr(dst1, src, cond); - } else { - ldr(dst1, src, cond); - ldr(dst2, src2, cond); + if ((src.am() == Offset) || (src.am() == NegOffset)) { + src2.set_offset(src2.offset() + 4); + if (dst1.is(src.rn())) { + ldr(dst2, src2, cond); + ldr(dst1, src, cond); + } else { + ldr(dst1, src, cond); + ldr(dst2, src2, cond); + } + } else { // PostIndex or NegPostIndex. + if (dst1.is(src.rn())) { + ldr(dst2, MemOperand(src.rn(), 4, Offset), cond); + ldr(dst1, src, cond); + } else { + src2.set_offset(src2.offset() - 4); + ldr(dst1, MemOperand(src.rn(), 4, PostIndex), cond); + ldr(dst2, src2, cond); + } } } } @@ -679,15 +694,25 @@ ASSERT_EQ(0, src1.code() % 2); ASSERT_EQ(src1.code() + 1, src2.code()); + // V8 does not use this addressing mode, so the fallback code + // below doesn't support it yet. + ASSERT((dst.am() != PreIndex) && (dst.am() != NegPreIndex)); + // Generate two str instructions if strd is not available. if (CpuFeatures::IsSupported(ARMv7)) { CpuFeatures::Scope scope(ARMv7); strd(src1, src2, dst, cond); } else { MemOperand dst2(dst); - dst2.set_offset(dst2.offset() + 4); - str(src1, dst, cond); - str(src2, dst2, cond); + if ((dst.am() == Offset) || (dst.am() == NegOffset)) { + dst2.set_offset(dst2.offset() + 4); + str(src1, dst, cond); + str(src2, dst2, cond); + } else { // PostIndex or NegPostIndex. + dst2.set_offset(dst2.offset() - 4); + str(src1, MemOperand(dst.rn(), 4, PostIndex), cond); + str(src2, dst2, cond); + } } } -- v8-dev mailing list [email protected] http://groups.google.com/group/v8-dev
