Reviewers: fschneider,
Message:
this fixes a bug in Issue 7744014 (http://codereview.chromium.org/7744014/)
which you landed for me last week in r9014.
Description:
MIPS: Fixed a bug in a special case of MacroAssembler::Ext.
In mips32r1 mode the target register was not be properly set up when
shift_left
== 0.
BUG=
TEST=
Please review this at http://codereview.chromium.org/7777005/
Affected files:
M src/mips/macro-assembler-mips.cc
Index: src/mips/macro-assembler-mips.cc
diff --git a/src/mips/macro-assembler-mips.cc
b/src/mips/macro-assembler-mips.cc
index
dedea2a044a21eb4f5f0e181b038d26b43b844eb..8e4b8ef9737624a6f6d723acf08e752284c8adda
100644
--- a/src/mips/macro-assembler-mips.cc
+++ b/src/mips/macro-assembler-mips.cc
@@ -765,9 +765,7 @@ void MacroAssembler::Ext(Register rt,
// Move rs to rt and shift it left then right to get the
// desired bitfield on the right side and zeroes on the left.
int shift_left = 32 - (pos + size);
- if (shift_left > 0) {
- sll(rt, rs, shift_left);
- }
+ sll(rt, rs, shift_left); // Acts as a move if shift_left == 0.
int shift_right = 32 - size;
if (shift_right > 0) {
--
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