Revision: 10015
Author: [email protected]
Date: Thu Nov 17 05:31:26 2011
Log: MIPS: Fix for Ins macro-assembler instruction for non-mips32r2
platforms.
BUG=
TEST=
Review URL: http://codereview.chromium.org/8520023
Patch from Gergely Kis <[email protected]>.
http://code.google.com/p/v8/source/detail?r=10015
Modified:
/branches/bleeding_edge/src/mips/macro-assembler-mips.cc
=======================================
--- /branches/bleeding_edge/src/mips/macro-assembler-mips.cc Wed Nov 9
03:04:41 2011
+++ /branches/bleeding_edge/src/mips/macro-assembler-mips.cc Thu Nov 17
05:31:26 2011
@@ -910,34 +910,21 @@
uint16_t pos,
uint16_t size) {
ASSERT(pos < 32);
- ASSERT(pos + size < 32);
+ ASSERT(pos + size <= 32);
+ ASSERT(size != 0);
if (mips32r2) {
ins_(rt, rs, pos, size);
} else {
ASSERT(!rt.is(t8) && !rs.is(t8));
-
- srl(t8, rt, pos + size);
- // The left chunk from rt that needs to
- // be saved is on the right side of t8.
- sll(at, t8, pos + size);
- // The 'at' register now contains the left chunk on
- // the left (proper position) and zeroes.
- sll(t8, rt, 32 - pos);
- // t8 now contains the right chunk on the left and zeroes.
- srl(t8, t8, 32 - pos);
- // t8 now contains the right chunk on
- // the right (proper position) and zeroes.
- or_(rt, at, t8);
- // rt now contains the left and right chunks from the original rt
- // in their proper position and zeroes in the middle.
- sll(t8, rs, 32 - size);
- // t8 now contains the chunk from rs on the left and zeroes.
- srl(t8, t8, 32 - size - pos);
- // t8 now contains the original chunk from rs in
- // the middle (proper position).
- or_(rt, rt, t8);
- // rt now contains the result of the ins instruction in R2 mode.
+ Subu(at, zero_reg, Operand(1));
+ srl(at, at, 32 - size);
+ and_(t8, rs, at);
+ sll(t8, t8, pos);
+ sll(at, at, pos);
+ nor(at, at, zero_reg);
+ and_(at, rt, at);
+ or_(rt, t8, at);
}
}
--
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