Revision: 10644
Author: [email protected]
Date: Wed Feb 8 06:41:10 2012
Log: MIPS: Don't allow large immediates for certain instructions.
Some instructions can use >16 bit immediates if they represent a <=16 bit
signed value.
However some logical instructions (andi, xori, ori, lui) should always
treat the immediate value as unsigned.
This patch adds an ASSERT to these places and a minor change to
MacroAssembler::li to satisfy this.
BUG=
TEST=
Review URL: https://chromiumcodereview.appspot.com/9309077
Patch from Daniel Kalmar <[email protected]>.
http://code.google.com/p/v8/source/detail?r=10644
Modified:
/branches/bleeding_edge/src/mips/assembler-mips.cc
/branches/bleeding_edge/src/mips/macro-assembler-mips.cc
=======================================
--- /branches/bleeding_edge/src/mips/assembler-mips.cc Fri Jan 13 05:09:52
2012
+++ /branches/bleeding_edge/src/mips/assembler-mips.cc Wed Feb 8 06:41:10
2012
@@ -1245,6 +1245,7 @@
void Assembler::andi(Register rt, Register rs, int32_t j) {
+ ASSERT(is_uint16(j));
GenInstrImmediate(ANDI, rs, rt, j);
}
@@ -1255,6 +1256,7 @@
void Assembler::ori(Register rt, Register rs, int32_t j) {
+ ASSERT(is_uint16(j));
GenInstrImmediate(ORI, rs, rt, j);
}
@@ -1265,6 +1267,7 @@
void Assembler::xori(Register rt, Register rs, int32_t j) {
+ ASSERT(is_uint16(j));
GenInstrImmediate(XORI, rs, rt, j);
}
@@ -1445,6 +1448,7 @@
void Assembler::lui(Register rd, int32_t j) {
+ ASSERT(is_uint16(j));
GenInstrImmediate(LUI, zero_reg, rd, j);
}
=======================================
--- /branches/bleeding_edge/src/mips/macro-assembler-mips.cc Tue Jan 31
04:45:27 2012
+++ /branches/bleeding_edge/src/mips/macro-assembler-mips.cc Wed Feb 8
06:41:10 2012
@@ -771,18 +771,18 @@
} else if (!(j.imm32_ & kHiMask)) {
ori(rd, zero_reg, j.imm32_);
} else if (!(j.imm32_ & kImm16Mask)) {
- lui(rd, (j.imm32_ & kHiMask) >> kLuiShift);
+ lui(rd, (j.imm32_ >> kLuiShift) & kImm16Mask);
} else {
- lui(rd, (j.imm32_ & kHiMask) >> kLuiShift);
+ lui(rd, (j.imm32_ >> kLuiShift) & kImm16Mask);
ori(rd, rd, (j.imm32_ & kImm16Mask));
}
} else if (MustUseReg(j.rmode_) || gen2instr) {
if (MustUseReg(j.rmode_)) {
RecordRelocInfo(j.rmode_, j.imm32_);
}
- // We need always the same number of instructions as we may need to
patch
+ // We always need the same number of instructions as we may need to
patch
// this code to load another value which may need 2 instructions to
load.
- lui(rd, (j.imm32_ & kHiMask) >> kLuiShift);
+ lui(rd, (j.imm32_ >> kLuiShift) & kImm16Mask);
ori(rd, rd, (j.imm32_ & kImm16Mask));
}
}
--
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