Revision: 12737
Author: [email protected]
Date: Mon Oct 15 08:42:09 2012
Log: Simulate and disasm NOP on ARM
[email protected]
Review URL: https://chromiumcodereview.appspot.com/11116011
Patch from JF Bastien <[email protected]>.
http://code.google.com/p/v8/source/detail?r=12737
Modified:
/branches/bleeding_edge/src/arm/assembler-arm.cc
/branches/bleeding_edge/src/arm/constants-arm.h
/branches/bleeding_edge/src/arm/disasm-arm.cc
/branches/bleeding_edge/src/arm/simulator-arm.cc
=======================================
--- /branches/bleeding_edge/src/arm/assembler-arm.cc Mon Oct 15 08:19:36
2012
+++ /branches/bleeding_edge/src/arm/assembler-arm.cc Mon Oct 15 08:42:09
2012
@@ -2440,15 +2440,19 @@
// Pseudo instructions.
void Assembler::nop(int type) {
- // This is mov rx, rx.
- ASSERT(0 <= type && type <= 14); // mov pc, pc is not a nop.
+ // ARMv6{K/T2} and v7 have an actual NOP instruction but it serializes
+ // some of the CPU's pipeline and has to issue. Older ARM chips simply
used
+ // MOV Rx, Rx as NOP and it performs better even in newer CPUs.
+ // We therefore use MOV Rx, Rx, even on newer CPUs, and use Rx to encode
+ // a type.
+ ASSERT(0 <= type && type <= 14); // mov pc, pc isn't a nop.
emit(al | 13*B21 | type*B12 | type);
}
bool Assembler::IsNop(Instr instr, int type) {
+ ASSERT(0 <= type && type <= 14); // mov pc, pc isn't a nop.
// Check for mov rx, rx where x = type.
- ASSERT(0 <= type && type <= 14); // mov pc, pc is not a nop.
return instr == (al | 13*B21 | type*B12 | type);
}
=======================================
--- /branches/bleeding_edge/src/arm/constants-arm.h Mon Oct 15 08:19:36 2012
+++ /branches/bleeding_edge/src/arm/constants-arm.h Mon Oct 15 08:42:09 2012
@@ -686,6 +686,9 @@
&& (Bit(23) == 0)
&& (Bit(20) == 0)
&& ((Bit(7) == 0)); }
+
+ // Test for a nop instruction, which falls under type 1.
+ inline bool IsNopType1() const { return Bits(24, 0) == 0x0120F000; }
// Test for a stop instruction.
inline bool IsStop() const {
=======================================
--- /branches/bleeding_edge/src/arm/disasm-arm.cc Mon Oct 1 14:27:33 2012
+++ /branches/bleeding_edge/src/arm/disasm-arm.cc Mon Oct 15 08:42:09 2012
@@ -830,6 +830,8 @@
} else {
Unknown(instr); // not used by V8
}
+ } else if ((type == 1) && instr->IsNopType1()) {
+ Format(instr, "nop'cond");
} else {
switch (instr->OpcodeField()) {
case AND: {
=======================================
--- /branches/bleeding_edge/src/arm/simulator-arm.cc Mon Oct 15 08:19:36
2012
+++ /branches/bleeding_edge/src/arm/simulator-arm.cc Mon Oct 15 08:42:09
2012
@@ -2183,6 +2183,8 @@
PrintF("%08x\n", instr->InstructionBits());
UNIMPLEMENTED();
}
+ } else if ((type == 1) && instr->IsNopType1()) {
+ // NOP.
} else {
int rd = instr->RdValue();
int rn = instr->RnValue();
--
v8-dev mailing list
[email protected]
http://groups.google.com/group/v8-dev
