Revision: 12971
Author: [email protected]
Date: Thu Nov 15 04:41:35 2012
Log: MIPS: Add rotate-right instruction to hydrogen and use it instead
of bitwise operations of the form ((x >>> i) | (x << (32 - i))).
Port r12855 (be965042)
BUG=
TEST=
Review URL: https://chromiumcodereview.appspot.com/11293140
Patch from Akos Palfi <[email protected]>.
http://code.google.com/p/v8/source/detail?r=12971
Modified:
/branches/bleeding_edge/src/mips/lithium-codegen-mips.cc
/branches/bleeding_edge/src/mips/lithium-mips.cc
=======================================
--- /branches/bleeding_edge/src/mips/lithium-codegen-mips.cc Thu Nov 15
02:12:28 2012
+++ /branches/bleeding_edge/src/mips/lithium-codegen-mips.cc Thu Nov 15
04:41:35 2012
@@ -1148,6 +1148,9 @@
// No need to mask the right operand on MIPS, it is built into the
variable
// shift instructions.
switch (instr->op()) {
+ case Token::ROR:
+ __ Ror(result, left, Operand(ToRegister(right_op)));
+ break;
case Token::SAR:
__ srav(result, left, ToRegister(right_op));
break;
@@ -1169,6 +1172,13 @@
int value = ToInteger32(LConstantOperand::cast(right_op));
uint8_t shift_count = static_cast<uint8_t>(value & 0x1F);
switch (instr->op()) {
+ case Token::ROR:
+ if (shift_count != 0) {
+ __ Ror(result, left, Operand(shift_count));
+ } else {
+ __ Move(result, left);
+ }
+ break;
case Token::SAR:
if (shift_count != 0) {
__ sra(result, left, shift_count);
=======================================
--- /branches/bleeding_edge/src/mips/lithium-mips.cc Tue Nov 13 23:33:16
2012
+++ /branches/bleeding_edge/src/mips/lithium-mips.cc Thu Nov 15 04:41:35
2012
@@ -177,6 +177,7 @@
case Token::BIT_AND: return "bit-and-t";
case Token::BIT_OR: return "bit-or-t";
case Token::BIT_XOR: return "bit-xor-t";
+ case Token::ROR: return "ror-t";
case Token::SHL: return "sll-t";
case Token::SAR: return "sra-t";
case Token::SHR: return "srl-t";
--
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