Revision: 14355
Author: [email protected]
Date: Fri Apr 19 07:22:38 2013
Log: Update arm and mips simulator to also use cmath
Review URL: https://codereview.chromium.org/14241029
Patch from Jochen Eisinger <[email protected]>.
http://code.google.com/p/v8/source/detail?r=14355
Modified:
/branches/bleeding_edge/src/arm/simulator-arm.cc
/branches/bleeding_edge/src/mips/simulator-mips.cc
=======================================
--- /branches/bleeding_edge/src/arm/simulator-arm.cc Wed Apr 17 06:51:08
2013
+++ /branches/bleeding_edge/src/arm/simulator-arm.cc Fri Apr 19 07:22:38
2013
@@ -26,7 +26,7 @@
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#include <stdlib.h>
-#include <math.h>
+#include <cmath>
#include <cstdarg>
#include "v8.h"
@@ -1297,7 +1297,7 @@
// Support for VFP comparisons.
void Simulator::Compute_FPSCR_Flags(double val1, double val2) {
- if (isnan(val1) || isnan(val2)) {
+ if (std::isnan(val1) || std::isnan(val2)) {
n_flag_FPSCR_ = false;
z_flag_FPSCR_ = false;
c_flag_FPSCR_ = true;
@@ -1866,7 +1866,7 @@
double Simulator::canonicalizeNaN(double value) {
- return (FPSCR_default_NaN_mode_ && isnan(value)) ?
+ return (FPSCR_default_NaN_mode_ && std::isnan(value)) ?
FixedDoubleArray::canonical_not_the_hole_nan_as_double() : value;
}
@@ -2947,7 +2947,7 @@
// Raise exceptions for quiet NaNs if necessary.
if (instr->Bit(7) == 1) {
- if (isnan(dd_value)) {
+ if (std::isnan(dd_value)) {
inv_op_vfp_flag_ = true;
}
}
=======================================
--- /branches/bleeding_edge/src/mips/simulator-mips.cc Tue Apr 16 05:30:51
2013
+++ /branches/bleeding_edge/src/mips/simulator-mips.cc Fri Apr 19 07:22:38
2013
@@ -26,8 +26,8 @@
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#include <stdlib.h>
-#include <math.h>
#include <limits.h>
+#include <cmath>
#include <cstdarg>
#include "v8.h"
@@ -1155,7 +1155,7 @@
bool Simulator::set_fcsr_round_error(double original, double rounded) {
bool ret = false;
- if (!isfinite(original) || !isfinite(rounded)) {
+ if (!std::isfinite(original) || !std::isfinite(rounded)) {
set_fcsr_bit(kFCSRInvalidOpFlagBit, true);
ret = true;
}
@@ -2067,25 +2067,28 @@
set_fpu_register_double(fd_reg, sqrt(fs));
break;
case C_UN_D:
- set_fcsr_bit(fcsr_cc, isnan(fs) || isnan(ft));
+ set_fcsr_bit(fcsr_cc, std::isnan(fs) || std::isnan(ft));
break;
case C_EQ_D:
set_fcsr_bit(fcsr_cc, (fs == ft));
break;
case C_UEQ_D:
- set_fcsr_bit(fcsr_cc, (fs == ft) || (isnan(fs) ||
isnan(ft)));
+ set_fcsr_bit(fcsr_cc,
+ (fs == ft) || (std::isnan(fs) ||
std::isnan(ft)));
break;
case C_OLT_D:
set_fcsr_bit(fcsr_cc, (fs < ft));
break;
case C_ULT_D:
- set_fcsr_bit(fcsr_cc, (fs < ft) || (isnan(fs) || isnan(ft)));
+ set_fcsr_bit(fcsr_cc,
+ (fs < ft) || (std::isnan(fs) ||
std::isnan(ft)));
break;
case C_OLE_D:
set_fcsr_bit(fcsr_cc, (fs <= ft));
break;
case C_ULE_D:
- set_fcsr_bit(fcsr_cc, (fs <= ft) || (isnan(fs) ||
isnan(ft)));
+ set_fcsr_bit(fcsr_cc,
+ (fs <= ft) || (std::isnan(fs) ||
std::isnan(ft)));
break;
case CVT_W_D: // Convert double to word.
// Rounding modes are not yet supported.
--
--
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