Reviewers: danno, Jakob, palfia, kisg,
Message:
Danno, Jakob, PTAL, this is outside the mips dir, I need your review.
Description:
MIPS: Fix memory barriers for atomic operations.
Add barriers using MIPS 'sync' instructions as needed for SMP
systems.
BUG=246947
Please review this at https://codereview.chromium.org/15981017/
SVN Base: https://v8.googlecode.com/svn/branches/bleeding_edge
Affected files:
M src/atomicops_internals_mips_gcc.h
Index: src/atomicops_internals_mips_gcc.h
diff --git a/src/atomicops_internals_mips_gcc.h
b/src/atomicops_internals_mips_gcc.h
index
9498fd76e1478c83ebfa77f1f390983e72fa41e5..cb8f8b9d954e8cb37fa2d2f9c326607a846156f6
100644
--- a/src/atomicops_internals_mips_gcc.h
+++ b/src/atomicops_internals_mips_gcc.h
@@ -30,8 +30,6 @@
#ifndef V8_ATOMICOPS_INTERNALS_MIPS_GCC_H_
#define V8_ATOMICOPS_INTERNALS_MIPS_GCC_H_
-#define ATOMICOPS_COMPILER_BARRIER() __asm__
__volatile__("" : : : "memory")
-
namespace v8 {
namespace internal {
@@ -111,9 +109,9 @@ inline Atomic32 NoBarrier_AtomicIncrement(volatile
Atomic32* ptr,
inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
Atomic32 increment) {
- ATOMICOPS_COMPILER_BARRIER();
+ MemoryBarrier();
Atomic32 res = NoBarrier_AtomicIncrement(ptr, increment);
- ATOMICOPS_COMPILER_BARRIER();
+ MemoryBarrier();
return res;
}
@@ -126,19 +124,16 @@ inline Atomic32 Barrier_AtomicIncrement(volatile
Atomic32* ptr,
inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
Atomic32 old_value,
Atomic32 new_value) {
- ATOMICOPS_COMPILER_BARRIER();
Atomic32 res = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
- ATOMICOPS_COMPILER_BARRIER();
+ MemoryBarrier();
return res;
}
inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
Atomic32 old_value,
Atomic32 new_value) {
- ATOMICOPS_COMPILER_BARRIER();
- Atomic32 res = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
- ATOMICOPS_COMPILER_BARRIER();
- return res;
+ MemoryBarrier();
+ return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
}
inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
@@ -176,6 +171,4 @@ inline Atomic32 Release_Load(volatile const Atomic32*
ptr) {
} } // namespace v8::internal
-#undef ATOMICOPS_COMPILER_BARRIER
-
#endif // V8_ATOMICOPS_INTERNALS_MIPS_GCC_H_
--
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