LGTM (with a couple of nits)
https://chromiumcodereview.appspot.com/16109010/diff/11001/src/atomicops_internals_arm_gcc.h
File src/atomicops_internals_arm_gcc.h (right):
https://chromiumcodereview.appspot.com/16109010/diff/11001/src/atomicops_internals_arm_gcc.h#newcode50
src/atomicops_internals_arm_gcc.h:50: // it's completely un-needed on
these devices.
This comment is a bit confusing. I presume you mean memory barrier for
multi-threaded code, note that barriers can be required on single core
cpu for other uses (e.g. ensure the effect of cache maintenance is
visible).
https://chromiumcodereview.appspot.com/16109010/diff/11001/src/atomicops_internals_arm_gcc.h#newcode92
src/atomicops_internals_arm_gcc.h:92: // if (prev_value != old_value)
nit: if (prev_value == old_value)
https://chromiumcodereview.appspot.com/16109010/
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