Reviewers: Sven Panne, rossberg, Jakob, Michael Starzinger,
Message:
PTAL, red-only :-)
Description:
Drop unused rdtsc instruction.
We do not use rdtsc anywhere and we won't ever use that in the
future, as it is totally unusable with multicore and out of
order execution.
Please review this at https://codereview.chromium.org/23112016/
SVN Base: https://v8.googlecode.com/svn/branches/bleeding_edge
Affected files:
M src/flag-definitions.h
M src/ia32/assembler-ia32.h
M src/ia32/assembler-ia32.cc
M src/ia32/disasm-ia32.cc
M src/platform-posix.cc
M src/v8globals.h
M src/x64/assembler-x64.h
M src/x64/assembler-x64.cc
M src/x64/disasm-x64.cc
M test/cctest/test-disasm-ia32.cc
M test/cctest/test-disasm-x64.cc
Index: src/flag-definitions.h
diff --git a/src/flag-definitions.h b/src/flag-definitions.h
index
f5f2ef37f0223a487e5ce745efba813b89fbb1a7..aed8591331a315a45a9bd6690b1f5afb7d7eee39
100644
--- a/src/flag-definitions.h
+++ b/src/flag-definitions.h
@@ -356,8 +356,6 @@ DEFINE_bool(enable_sse4_1, true,
"enable use of SSE4.1 instructions if available")
DEFINE_bool(enable_cmov, true,
"enable use of CMOV instruction if available")
-DEFINE_bool(enable_rdtsc, true,
- "enable use of RDTSC instruction if available")
DEFINE_bool(enable_sahf, true,
"enable use of SAHF instruction if available (X64 only)")
DEFINE_bool(enable_vfp3, ENABLE_VFP3_DEFAULT,
Index: src/ia32/assembler-ia32.cc
diff --git a/src/ia32/assembler-ia32.cc b/src/ia32/assembler-ia32.cc
index
37218e54dd99bf6e40b83cd04ad5a746d353a42e..ab4e0a43d18597bd157fe06bdd96b3caf6b9aaf4
100644
--- a/src/ia32/assembler-ia32.cc
+++ b/src/ia32/assembler-ia32.cc
@@ -1310,14 +1310,6 @@ void Assembler::nop() {
}
-void Assembler::rdtsc() {
- ASSERT(IsEnabled(RDTSC));
- EnsureSpace ensure_space(this);
- EMIT(0x0F);
- EMIT(0x31);
-}
-
-
void Assembler::ret(int imm16) {
EnsureSpace ensure_space(this);
ASSERT(is_uint16(imm16));
Index: src/ia32/assembler-ia32.h
diff --git a/src/ia32/assembler-ia32.h b/src/ia32/assembler-ia32.h
index
c10293783947ba2a1f2479312d45737186e31fac..d6b6dab44c0ccfa854e03429fe88dda4ecace176
100644
--- a/src/ia32/assembler-ia32.h
+++ b/src/ia32/assembler-ia32.h
@@ -537,7 +537,6 @@ class CpuFeatures : public AllStatic {
if (f == SSE3 && !FLAG_enable_sse3) return false;
if (f == SSE4_1 && !FLAG_enable_sse4_1) return false;
if (f == CMOV && !FLAG_enable_cmov) return false;
- if (f == RDTSC && !FLAG_enable_rdtsc) return false;
return (supported_ & (static_cast<uint64_t>(1) << f)) != 0;
}
@@ -870,7 +869,6 @@ class Assembler : public AssemblerBase {
void hlt();
void int3();
void nop();
- void rdtsc();
void ret(int imm16);
// Label operations & relative jumps (PPUM Appendix D)
Index: src/ia32/disasm-ia32.cc
diff --git a/src/ia32/disasm-ia32.cc b/src/ia32/disasm-ia32.cc
index
c43f11c00e966590ca3c92f0ac75ab0a45a3ca40..892b66e814a5b6e82cabf1029db5f7ec013edf46
100644
--- a/src/ia32/disasm-ia32.cc
+++ b/src/ia32/disasm-ia32.cc
@@ -862,7 +862,6 @@ static const char* F0Mnem(byte f0byte) {
switch (f0byte) {
case 0x18: return "prefetch";
case 0xA2: return "cpuid";
- case 0x31: return "rdtsc";
case 0xBE: return "movsx_b";
case 0xBF: return "movsx_w";
case 0xB6: return "movzx_b";
Index: src/platform-posix.cc
diff --git a/src/platform-posix.cc b/src/platform-posix.cc
index
13b819bd1e79c1452979961fd082c2af73171e56..f7ab8a124be3eaff1d9aa762da8a77d6f548874f
100644
--- a/src/platform-posix.cc
+++ b/src/platform-posix.cc
@@ -83,7 +83,7 @@ uint64_t OS::CpuFeaturesImpliedByPlatform() {
// Mac OS X requires all these to install so we can assume they are
present.
// These constants are defined by the CPUid instructions.
const uint64_t one = 1;
- return (one << SSE2) | (one << CMOV) | (one << RDTSC) | (one << CPUID);
+ return (one << SSE2) | (one << CMOV) | (one << CPUID);
#else
return 0; // Nothing special about the other systems.
#endif
Index: src/v8globals.h
diff --git a/src/v8globals.h b/src/v8globals.h
index
6ec75478875af0e4cfc87cdff84c7348176d5960..00693fa33cd17a866a3d00435a65b69ca982c468
100644
--- a/src/v8globals.h
+++ b/src/v8globals.h
@@ -438,7 +438,6 @@ enum CpuFeature { SSE4_1 = 32 + 19, // x86
SSE3 = 32 + 0, // x86
SSE2 = 26, // x86
CMOV = 15, // x86
- RDTSC = 4, // x86
CPUID = 10, // x86
VFP3 = 1, // ARM
ARMv7 = 2, // ARM
Index: src/x64/assembler-x64.cc
diff --git a/src/x64/assembler-x64.cc b/src/x64/assembler-x64.cc
index
8969d89a6a75db3b8a021ea666db81cffb4c9033..68d2c05edc526626976de2c7e5c6a7a0f6d6a8f6
100644
--- a/src/x64/assembler-x64.cc
+++ b/src/x64/assembler-x64.cc
@@ -1919,13 +1919,6 @@ void Assembler::pushfq() {
}
-void Assembler::rdtsc() {
- EnsureSpace ensure_space(this);
- emit(0x0F);
- emit(0x31);
-}
-
-
void Assembler::ret(int imm16) {
EnsureSpace ensure_space(this);
ASSERT(is_uint16(imm16));
Index: src/x64/assembler-x64.h
diff --git a/src/x64/assembler-x64.h b/src/x64/assembler-x64.h
index
4e36b6e4bc4062ead3023e978af5e2115b7c99db..d92849ab0d6e92ea241987af4bf811621636b837
100644
--- a/src/x64/assembler-x64.h
+++ b/src/x64/assembler-x64.h
@@ -475,7 +475,6 @@ class CpuFeatures : public AllStatic {
if (f == SSE3 && !FLAG_enable_sse3) return false;
if (f == SSE4_1 && !FLAG_enable_sse4_1) return false;
if (f == CMOV && !FLAG_enable_cmov) return false;
- if (f == RDTSC && !FLAG_enable_rdtsc) return false;
if (f == SAHF && !FLAG_enable_sahf) return false;
return (supported_ & (static_cast<uint64_t>(1) << f)) != 0;
}
@@ -1176,7 +1175,6 @@ class Assembler : public AssemblerBase {
void hlt();
void int3();
void nop();
- void rdtsc();
void ret(int imm16);
void setcc(Condition cc, Register reg);
Index: src/x64/disasm-x64.cc
diff --git a/src/x64/disasm-x64.cc b/src/x64/disasm-x64.cc
index
eefa70372ec4c8ac344665cecb6c52d16479e99d..e9ace153c4e26522d8db258e73b4a32d95980c8d
100644
--- a/src/x64/disasm-x64.cc
+++ b/src/x64/disasm-x64.cc
@@ -1229,8 +1229,8 @@ int DisassemblerX64::TwoByteOpcodeInstruction(byte*
data) {
current += PrintRightXMMOperand(current);
AppendToBuffer(", %s", NameOfXMMRegister(regop));
- } else if (opcode == 0xA2 || opcode == 0x31) {
- // RDTSC or CPUID
+ } else if (opcode == 0xA2) {
+ // CPUID
AppendToBuffer("%s", mnemonic);
} else if ((opcode & 0xF0) == 0x40) {
@@ -1294,8 +1294,6 @@ const char* DisassemblerX64::TwoByteMnemonic(byte
opcode) {
return "nop";
case 0x2A: // F2/F3 prefix.
return "cvtsi2s";
- case 0x31:
- return "rdtsc";
case 0x51: // F2 prefix.
return "sqrtsd";
case 0x58: // F2 prefix.
Index: test/cctest/test-disasm-ia32.cc
diff --git a/test/cctest/test-disasm-ia32.cc
b/test/cctest/test-disasm-ia32.cc
index
14447b2c45f435b82f1d2ec6d946d5ca5cff6f8a..90469e5358d4b57da3fdfa2c00338b015db8055c
100644
--- a/test/cctest/test-disasm-ia32.cc
+++ b/test/cctest/test-disasm-ia32.cc
@@ -104,11 +104,6 @@ TEST(DisasmIa320) {
CpuFeatureScope fscope(&assm, CPUID);
__ cpuid();
}
- {
- CHECK(CpuFeatures::IsSupported(RDTSC));
- CpuFeatureScope fscope(&assm, RDTSC);
- __ rdtsc();
- }
__ movsx_b(edx, ecx);
__ movsx_w(edx, ecx);
__ movzx_b(edx, ecx);
Index: test/cctest/test-disasm-x64.cc
diff --git a/test/cctest/test-disasm-x64.cc b/test/cctest/test-disasm-x64.cc
index
1c7f416392e32d840d26758c4103b9bcab42be02..1ff9fd336bd9380bfb736bbc8846c2133f648daf
100644
--- a/test/cctest/test-disasm-x64.cc
+++ b/test/cctest/test-disasm-x64.cc
@@ -95,11 +95,6 @@ TEST(DisasmX64) {
CpuFeatures::Scope fscope(CPUID);
__ cpuid();
}
- {
- CHECK(CpuFeatures::IsSupported(RDTSC));
- CpuFeatures::Scope fscope(RDTSC);
- __ rdtsc();
- }
__ movsxbq(rdx, Operand(rcx, 0));
__ movsxwq(rdx, Operand(rcx, 0));
__ movzxbl(rdx, Operand(rcx, 0));
--
--
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