Reviewers: danno, Paul Lind, Jakob, kisg,
Message:
PTAL
Description:
MIPS: Enable aligned keyed stores and loads for double arrays.
Provide ~20% performance improvement in Navier-Stokes benchmark, by using
true load/store double (ldc1/sdc1) instructions.
These instructions require double-aligned memory address.
Since doubles are not generally aligned in v8, we historically have used
a workaround using a pair of 32-bit loads/stores (lwc1/swc1), which is slow.
This CL requires FixedDoubleArrays to be aligned in all cases, which is
achieved
via these related CL's: https://chromiumcodereview.appspot.com/35103002,
https://chromiumcodereview.appspot.com/35133002,
https://chromiumcodereview.appspot.com/35313002.
TEST=
BUG=
Please review this at https://codereview.chromium.org/35463002/
SVN Base: https://v8.googlecode.com/svn/branches/bleeding_edge
Affected files (+26, -14 lines):
M src/flag-definitions.h
M src/mips/assembler-mips.h
M src/mips/assembler-mips.cc
M src/mips/lithium-codegen-mips.cc
Index: src/flag-definitions.h
diff --git a/src/flag-definitions.h b/src/flag-definitions.h
index
9fff5524ac7e871d375044ad4b3108a12e9ab8ff..cbefa97340e8561041104e5cf0c9d2dd4d574cd7
100644
--- a/src/flag-definitions.h
+++ b/src/flag-definitions.h
@@ -403,6 +403,8 @@ DEFINE_bool(enable_32dregs, ENABLE_32DREGS_DEFAULT,
"enable use of d16-d31 registers on ARM - this requires VFP3")
DEFINE_bool(enable_vldr_imm, false,
"enable use of constant pools for double immediate (ARM only)")
+DEFINE_bool(enable_aligned_doubles, true,
+ "enable use of ldc1/sdc1 for double accessses (MIPS only)")
// bootstrapper.cc
DEFINE_string(expose_natives_as, NULL, "expose natives in global object")
Index: src/mips/assembler-mips.cc
diff --git a/src/mips/assembler-mips.cc b/src/mips/assembler-mips.cc
index
0972a8295cbe40ab049649d9035c783f3cf42e8d..362bf9eca0186284dbf8a187671fca1d3c4a3e2a
100644
--- a/src/mips/assembler-mips.cc
+++ b/src/mips/assembler-mips.cc
@@ -1630,13 +1630,17 @@ void Assembler::lwc1(FPURegister fd, const
MemOperand& src) {
}
-void Assembler::ldc1(FPURegister fd, const MemOperand& src) {
+void Assembler::ldc1(FPURegister fd, const MemOperand& src, bool aligned) {
// Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
// load to two 32-bit loads.
- GenInstrImmediate(LWC1, src.rm(), fd, src.offset_);
- FPURegister nextfpreg;
- nextfpreg.setcode(fd.code() + 1);
- GenInstrImmediate(LWC1, src.rm(), nextfpreg, src.offset_ + 4);
+ if (aligned) {
+ GenInstrImmediate(LDC1, src.rm(), fd, src.offset_);
+ } else {
+ GenInstrImmediate(LWC1, src.rm(), fd, src.offset_);
+ FPURegister nextfpreg;
+ nextfpreg.setcode(fd.code() + 1);
+ GenInstrImmediate(LWC1, src.rm(), nextfpreg, src.offset_ + 4);
+ }
}
@@ -1645,13 +1649,17 @@ void Assembler::swc1(FPURegister fd, const
MemOperand& src) {
}
-void Assembler::sdc1(FPURegister fd, const MemOperand& src) {
+void Assembler::sdc1(FPURegister fd, const MemOperand& src, bool aligned) {
// Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
// store to two 32-bit stores.
- GenInstrImmediate(SWC1, src.rm(), fd, src.offset_);
- FPURegister nextfpreg;
- nextfpreg.setcode(fd.code() + 1);
- GenInstrImmediate(SWC1, src.rm(), nextfpreg, src.offset_ + 4);
+ if (aligned) {
+ GenInstrImmediate(SDC1, src.rm(), fd, src.offset_);
+ } else {
+ GenInstrImmediate(SWC1, src.rm(), fd, src.offset_);
+ FPURegister nextfpreg;
+ nextfpreg.setcode(fd.code() + 1);
+ GenInstrImmediate(SWC1, src.rm(), nextfpreg, src.offset_ + 4);
+ }
}
Index: src/mips/assembler-mips.h
diff --git a/src/mips/assembler-mips.h b/src/mips/assembler-mips.h
index
2468c3c340c7b8a9ec5dfe331b0b3ae0d2f6a941..8058fc8db9eb43134349ff833b449e381125a97e
100644
--- a/src/mips/assembler-mips.h
+++ b/src/mips/assembler-mips.h
@@ -755,10 +755,10 @@ class Assembler : public AssemblerBase {
// Load, store, and move.
void lwc1(FPURegister fd, const MemOperand& src);
- void ldc1(FPURegister fd, const MemOperand& src);
+ void ldc1(FPURegister fd, const MemOperand& src, bool aligned = false);
void swc1(FPURegister fs, const MemOperand& dst);
- void sdc1(FPURegister fs, const MemOperand& dst);
+ void sdc1(FPURegister fs, const MemOperand& dst, bool aligned = false);
void mtc1(Register rt, FPURegister fs);
void mfc1(Register rt, FPURegister fs);
Index: src/mips/lithium-codegen-mips.cc
diff --git a/src/mips/lithium-codegen-mips.cc
b/src/mips/lithium-codegen-mips.cc
index
2c6e5a501af061844956d05a03fc01884f993481..3936b075e1b00cdf3e6cd5dae03ca4c5e7f2db6b
100644
--- a/src/mips/lithium-codegen-mips.cc
+++ b/src/mips/lithium-codegen-mips.cc
@@ -3095,6 +3095,7 @@ void
LCodeGen::DoLoadKeyedFixedDoubleArray(LLoadKeyed* instr) {
Register key = no_reg;
DoubleRegister result = ToDoubleRegister(instr->result());
Register scratch = scratch0();
+ bool aligned = FLAG_enable_aligned_doubles;
int element_size_shift = ElementsKindToShiftSize(FAST_DOUBLE_ELEMENTS);
@@ -3118,7 +3119,7 @@ void
LCodeGen::DoLoadKeyedFixedDoubleArray(LLoadKeyed* instr) {
__ Addu(scratch, scratch, at);
}
- __ ldc1(result, MemOperand(scratch));
+ __ ldc1(result, MemOperand(scratch), aligned);
if (instr->hydrogen()->RequiresHoleCheck()) {
__ lw(scratch, MemOperand(scratch, sizeof(kHoleNanLower32)));
@@ -4301,6 +4302,7 @@ void
LCodeGen::DoStoreKeyedFixedDoubleArray(LStoreKeyed* instr) {
DoubleRegister double_scratch = double_scratch0();
bool key_is_constant = instr->key()->IsConstantOperand();
Label not_nan, done;
+ bool aligned = FLAG_enable_aligned_doubles;
// Calculate the effective address of the slot in the array to store the
// double value.
@@ -4339,7 +4341,7 @@ void
LCodeGen::DoStoreKeyedFixedDoubleArray(LStoreKeyed* instr) {
__ bind(¬_nan);
__ sdc1(value, MemOperand(scratch, instr->additional_index() <<
- element_size_shift));
+ element_size_shift), aligned);
__ bind(&done);
}
--
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