Reviewers: Sven Panne, haitao.feng,
Description:
Introduce orps for IA32/X64
BUG=
Please review this at https://codereview.chromium.org/53573004/
SVN Base: git://github.com/v8/v8.git@upstream
Affected files (+64, -27 lines):
M src/ia32/assembler-ia32.h
M src/ia32/assembler-ia32.cc
M src/ia32/codegen-ia32.cc
M src/ia32/disasm-ia32.cc
M src/ia32/lithium-codegen-ia32.cc
M src/ia32/lithium-gap-resolver-ia32.cc
M src/x64/assembler-x64.h
M src/x64/assembler-x64.cc
M src/x64/disasm-x64.cc
M src/x64/lithium-codegen-x64.cc
M src/x64/lithium-gap-resolver-x64.cc
M test/cctest/test-disasm-ia32.cc
M test/cctest/test-disasm-x64.cc
Index: src/ia32/assembler-ia32.cc
diff --git a/src/ia32/assembler-ia32.cc b/src/ia32/assembler-ia32.cc
index
0557ed885310beb876d7946f3b1d60e1e230cfb1..40345d8646553b465dee847c82e059ae5188c6eb
100644
--- a/src/ia32/assembler-ia32.cc
+++ b/src/ia32/assembler-ia32.cc
@@ -2059,6 +2059,22 @@ void Assembler::xorpd(XMMRegister dst, XMMRegister
src) {
}
+void Assembler::andps(XMMRegister dst, XMMRegister src) {
+ EnsureSpace ensure_space(this);
+ EMIT(0x0F);
+ EMIT(0x54);
+ emit_sse_operand(dst, src);
+}
+
+
+void Assembler::orps(XMMRegister dst, XMMRegister src) {
+ EnsureSpace ensure_space(this);
+ EMIT(0x0F);
+ EMIT(0x56);
+ emit_sse_operand(dst, src);
+}
+
+
void Assembler::xorps(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
@@ -2344,14 +2360,6 @@ void Assembler::extractps(Register dst, XMMRegister
src, byte imm8) {
}
-void Assembler::andps(XMMRegister dst, XMMRegister src) {
- EnsureSpace ensure_space(this);
- EMIT(0x0F);
- EMIT(0x54);
- emit_sse_operand(dst, src);
-}
-
-
void Assembler::pand(XMMRegister dst, XMMRegister src) {
ASSERT(IsEnabled(SSE2));
EnsureSpace ensure_space(this);
Index: src/ia32/assembler-ia32.h
diff --git a/src/ia32/assembler-ia32.h b/src/ia32/assembler-ia32.h
index
f46c6478dbf02dc9033b5bcb873623db7cda662d..57f496f2dd6a9e4862a836d656da0fe7f4d9156c
100644
--- a/src/ia32/assembler-ia32.h
+++ b/src/ia32/assembler-ia32.h
@@ -1020,6 +1020,7 @@ class Assembler : public AssemblerBase {
// SSE instructions
void andps(XMMRegister dst, XMMRegister src);
void xorps(XMMRegister dst, XMMRegister src);
+ void orps(XMMRegister dst, XMMRegister src);
// SSE2 instructions
void cvttss2si(Register dst, const Operand& src);
Index: src/ia32/codegen-ia32.cc
diff --git a/src/ia32/codegen-ia32.cc b/src/ia32/codegen-ia32.cc
index
d09a85f8b10c37e8a56fcde32760d395a50fb52b..ab4029da1197990a4d80a041db416a3aa7dd0894
100644
--- a/src/ia32/codegen-ia32.cc
+++ b/src/ia32/codegen-ia32.cc
@@ -1110,7 +1110,7 @@ void MathExpGenerator::EmitMathExp(MacroAssembler*
masm,
__ pshufd(input, input, static_cast<uint8_t>(0xe1)); // Order: 11 10 00
01
__ movsd(double_scratch, Operand::StaticArray(
temp2, times_8, ExternalReference::math_exp_log_table()));
- __ por(input, double_scratch);
+ __ orps(input, double_scratch);
__ mulsd(result, input);
__ bind(&done);
}
Index: src/ia32/disasm-ia32.cc
diff --git a/src/ia32/disasm-ia32.cc b/src/ia32/disasm-ia32.cc
index
13cf6bc49a5ec67663168fedf1da84f951711553..4e4d552526a140d0a0cdeac1f179ad4a5e89be68
100644
--- a/src/ia32/disasm-ia32.cc
+++ b/src/ia32/disasm-ia32.cc
@@ -1050,6 +1050,14 @@ int
DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer,
NameOfXMMRegister(regop),
NameOfXMMRegister(rm));
data++;
+ } else if (f0byte == 0x56) {
+ data += 2;
+ int mod, regop, rm;
+ get_modrm(*data, &mod, ®op, &rm);
+ AppendToBuffer("orps %s,%s",
+ NameOfXMMRegister(regop),
+ NameOfXMMRegister(rm));
+ data++;
} else if (f0byte == 0x57) {
data += 2;
int mod, regop, rm;
Index: src/ia32/lithium-codegen-ia32.cc
diff --git a/src/ia32/lithium-codegen-ia32.cc
b/src/ia32/lithium-codegen-ia32.cc
index
042a47080895f340c98feabba695b346f1f548a5..ee1995b7773ec584faa61a3738a0df937eaaf365
100644
--- a/src/ia32/lithium-codegen-ia32.cc
+++ b/src/ia32/lithium-codegen-ia32.cc
@@ -1958,7 +1958,7 @@ void LCodeGen::DoConstantD(LConstantD* instr) {
XMMRegister xmm_scratch = double_scratch0();
__ Set(temp, Immediate(lower));
__ movd(xmm_scratch, Operand(temp));
- __ por(res, xmm_scratch);
+ __ orps(res, xmm_scratch);
}
}
}
@@ -2184,7 +2184,7 @@ void LCodeGen::DoMathMinMax(LMathMinMax* instr) {
__ ucomisd(left_reg, left_reg); // NaN check.
__ j(parity_even, &return_left, Label::kNear); // left == NaN.
__ bind(&return_right);
- __ movsd(left_reg, right_reg);
+ __ movaps(left_reg, right_reg);
__ bind(&return_left);
}
@@ -3995,7 +3995,7 @@ void LCodeGen::DoMathRound(LMathRound* instr) {
// CVTTSD2SI rounds towards zero, we use ceil(x - (-0.5)) and then
// compare and compensate.
- __ movsd(input_temp, input_reg); // Do not alter input_reg.
+ __ movaps(input_temp, input_reg); // Do not alter input_reg.
__ subsd(input_temp, xmm_scratch);
__ cvttsd2si(output_reg, Operand(input_temp));
// Catch minint due to overflow, and to prevent overflow when
compensating.
Index: src/ia32/lithium-gap-resolver-ia32.cc
diff --git a/src/ia32/lithium-gap-resolver-ia32.cc
b/src/ia32/lithium-gap-resolver-ia32.cc
index
2b2126af9d1449acce2b90686e877ccfd86b6b01..d621bd261d65879136ea500751c96374101bd231
100644
--- a/src/ia32/lithium-gap-resolver-ia32.cc
+++ b/src/ia32/lithium-gap-resolver-ia32.cc
@@ -488,7 +488,7 @@ void LGapResolver::EmitSwap(int index) {
cgen_->ToOperand(source->IsDoubleRegister() ? destination :
source);
__ movsd(xmm0, other);
__ movsd(other, reg);
- __ movsd(reg, Operand(xmm0));
+ __ movaps(reg, xmm0);
} else if (source->IsDoubleStackSlot() &&
destination->IsDoubleStackSlot()) {
CpuFeatureScope scope(cgen_->masm(), SSE2);
// Double-width memory-to-memory. Spill on demand to use a general
Index: src/x64/assembler-x64.cc
diff --git a/src/x64/assembler-x64.cc b/src/x64/assembler-x64.cc
index
dcb9fa562159b8e33f2cfff8b7ffcf205c57b77e..99e2ad42c861cc79163edabb868107df6810d477
100644
--- a/src/x64/assembler-x64.cc
+++ b/src/x64/assembler-x64.cc
@@ -2487,6 +2487,24 @@ void Assembler::andps(XMMRegister dst, XMMRegister
src) {
}
+void Assembler::orps(XMMRegister dst, XMMRegister src) {
+ EnsureSpace ensure_space(this);
+ emit_optional_rex_32(dst, src);
+ emit(0x0F);
+ emit(0x56);
+ emit_sse_operand(dst, src);
+}
+
+
+void Assembler::xorps(XMMRegister dst, XMMRegister src) {
+ EnsureSpace ensure_space(this);
+ emit_optional_rex_32(dst, src);
+ emit(0x0F);
+ emit(0x57);
+ emit_sse_operand(dst, src);
+}
+
+
// SSE 2 operations.
void Assembler::movd(XMMRegister dst, Register src) {
@@ -2918,15 +2936,6 @@ void Assembler::xorpd(XMMRegister dst, XMMRegister
src) {
}
-void Assembler::xorps(XMMRegister dst, XMMRegister src) {
- EnsureSpace ensure_space(this);
- emit_optional_rex_32(dst, src);
- emit(0x0F);
- emit(0x57);
- emit_sse_operand(dst, src);
-}
-
-
void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit(0xF2);
Index: src/x64/assembler-x64.h
diff --git a/src/x64/assembler-x64.h b/src/x64/assembler-x64.h
index
508c62211237f61d7f78198db4730e9848718064..584b3a51e8fafa412a2fde6eb7dc8b632923638d
100644
--- a/src/x64/assembler-x64.h
+++ b/src/x64/assembler-x64.h
@@ -1355,8 +1355,9 @@ class Assembler : public AssemblerBase {
void cvttss2si(Register dst, XMMRegister src);
void cvtlsi2ss(XMMRegister dst, Register src);
- void xorps(XMMRegister dst, XMMRegister src);
void andps(XMMRegister dst, XMMRegister src);
+ void orps(XMMRegister dst, XMMRegister src);
+ void xorps(XMMRegister dst, XMMRegister src);
void movmskps(Register dst, XMMRegister src);
Index: src/x64/disasm-x64.cc
diff --git a/src/x64/disasm-x64.cc b/src/x64/disasm-x64.cc
index
7735b552fed75bd666a767de4b909d504f6f5862..70d410d422e64fc4203a9d7598e1a173165af867
100644
--- a/src/x64/disasm-x64.cc
+++ b/src/x64/disasm-x64.cc
@@ -1261,12 +1261,19 @@ int DisassemblerX64::TwoByteOpcodeInstruction(byte*
data) {
current += PrintOperands(idesc.mnem, idesc.op_order_, current);
} else if (opcode == 0x54) {
- // xorps xmm, xmm/m128
+ // andps xmm, xmm/m128
int mod, regop, rm;
get_modrm(*current, &mod, ®op, &rm);
AppendToBuffer("andps %s,", NameOfXMMRegister(regop));
current += PrintRightXMMOperand(current);
+ } else if (opcode == 0x56) {
+ // orps xmm, xmm/m128
+ int mod, regop, rm;
+ get_modrm(*current, &mod, ®op, &rm);
+ AppendToBuffer("orps %s,", NameOfXMMRegister(regop));
+ current += PrintRightXMMOperand(current);
+
} else if (opcode == 0x57) {
// xorps xmm, xmm/m128
int mod, regop, rm;
Index: src/x64/lithium-codegen-x64.cc
diff --git a/src/x64/lithium-codegen-x64.cc b/src/x64/lithium-codegen-x64.cc
index
85895b39039d2eb460e4f9bd828c781c1cbd9830..817b183888af28b7345c96e459d57bf5d90fd6a0
100644
--- a/src/x64/lithium-codegen-x64.cc
+++ b/src/x64/lithium-codegen-x64.cc
@@ -1771,7 +1771,7 @@ void LCodeGen::DoMathMinMax(LMathMinMax* instr) {
__ j(not_equal, &return_left, Label::kNear); // left == right != 0.
// At this point, both left and right are either 0 or -0.
if (operation == HMathMinMax::kMathMin) {
- __ orpd(left_reg, right_reg);
+ __ orps(left_reg, right_reg);
} else {
// Since we operate on +0 and/or -0, addsd and andsd have the same
effect.
__ addsd(left_reg, right_reg);
@@ -1782,7 +1782,7 @@ void LCodeGen::DoMathMinMax(LMathMinMax* instr) {
__ ucomisd(left_reg, left_reg); // NaN check.
__ j(parity_even, &return_left, Label::kNear);
__ bind(&return_right);
- __ movsd(left_reg, right_reg);
+ __ movaps(left_reg, right_reg);
__ bind(&return_left);
}
Index: src/x64/lithium-gap-resolver-x64.cc
diff --git a/src/x64/lithium-gap-resolver-x64.cc
b/src/x64/lithium-gap-resolver-x64.cc
index
8d1c2a2835c1614990ff2e6be01205d81bf57e7f..01cfb1232b8c866baf927a3385a1c584e677891b
100644
--- a/src/x64/lithium-gap-resolver-x64.cc
+++ b/src/x64/lithium-gap-resolver-x64.cc
@@ -305,7 +305,7 @@ void LGapResolver::EmitSwap(int index) {
Operand other_operand = cgen_->ToOperand(other);
__ movsd(xmm0, other_operand);
__ movsd(other_operand, reg);
- __ movsd(reg, xmm0);
+ __ movaps(reg, xmm0);
} else {
// No other combinations are possible.
Index: test/cctest/test-disasm-ia32.cc
diff --git a/test/cctest/test-disasm-ia32.cc
b/test/cctest/test-disasm-ia32.cc
index
301545c6c4a59bb5e7b394eb3580ac293e421913..7f9a6332ac1d6cd6722a94c1ac78c97de6a3c585
100644
--- a/test/cctest/test-disasm-ia32.cc
+++ b/test/cctest/test-disasm-ia32.cc
@@ -371,6 +371,7 @@ TEST(DisasmIa320) {
__ cmpltsd(xmm0, xmm1);
__ andps(xmm0, xmm1);
+ __ orps(xmm0, xmm1);
__ andpd(xmm0, xmm1);
__ psllq(xmm0, 17);
__ psllq(xmm0, xmm1);
Index: test/cctest/test-disasm-x64.cc
diff --git a/test/cctest/test-disasm-x64.cc b/test/cctest/test-disasm-x64.cc
index
8fd036956f368a0473f5ffeca5d25c5ed20c3d49..9fe73dea020b70609b84fa3a51a12d259e9afe5f
100644
--- a/test/cctest/test-disasm-x64.cc
+++ b/test/cctest/test-disasm-x64.cc
@@ -343,6 +343,8 @@ TEST(DisasmX64) {
__ movaps(xmm0, xmm1);
__ andps(xmm0, xmm1);
+ __ orps(xmm0, xmm1);
+ __ xorps(xmm0, xmm1);
}
// SSE 2 instructions
{
--
--
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