The OSR entry machinery changed a lot since your branch. The overall idea is
that the OSR entry is actually a second prologue for the function, and the
optimized frame actually subsumes the unoptimized frame.
I'll try to find representative CLs for the entrypoint changes on ARM and
IA32,
but here are general comments.
https://codereview.chromium.org/145713002/diff/110001/src/a64/builtins-a64.cc
File src/a64/builtins-a64.cc (right):
https://codereview.chromium.org/145713002/diff/110001/src/a64/builtins-a64.cc#newcode947
src/a64/builtins-a64.cc:947: __
CallRuntime(Runtime::kCompileForOnStackReplacement, 1);
This runtime call no longer returns the AST to indicate a successful
compile, but instead returns an actual code object, which one should
check against NULL (i.e. SMI 0). If non-null, then this code should
compute the OSR entry offset and jump directly to that.
https://codereview.chromium.org/145713002/diff/110001/src/a64/lithium-a64.cc
File src/a64/lithium-a64.cc (right):
https://codereview.chromium.org/145713002/diff/110001/src/a64/lithium-a64.cc#newcode2460
src/a64/lithium-a64.cc:2460: }
You will need to define these OSR values in exactly the right spill slot
so that the register allocator maps them to the correct location in the
frame. See the arm port for reference.
https://codereview.chromium.org/145713002/diff/110001/src/a64/lithium-codegen-a64.cc
File src/a64/lithium-codegen-a64.cc (right):
https://codereview.chromium.org/145713002/diff/110001/src/a64/lithium-codegen-a64.cc#newcode1928
src/a64/lithium-codegen-a64.cc:1928: if (osr_pc_offset_ == -1)
osr_pc_offset_ = masm()->pc_offset();
You should have a subroutine like DoGenerateOsrPrologue() that roughly
defines a new prologue for the function; see the arm port for reference.
Basically, this prologue must set up the frame, because the builtin will
jump directly into the middle of this code from the unoptimized code.
https://codereview.chromium.org/145713002/
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