Reviewers: ulan, Sven Panne,
Message:
A fix for the problem described here:
https://groups.google.com/forum/#!topic/v8-users/tSz5GBOEmqM
Description:
ARM: Fix Q register encoding
Fix Q register encoding for registers other than Q0. Also, fix value in
NeonSize
enumeration.
BUG=
Please review this at https://codereview.chromium.org/207523005/
SVN Base: https://v8.googlecode.com/svn/branches/bleeding_edge
Affected files (+35, -9 lines):
M src/arm/assembler-arm.h
M src/arm/constants-arm.h
M src/arm/disasm-arm.cc
M src/arm/simulator-arm.cc
M test/cctest/test-assembler-arm.cc
M test/cctest/test-disasm-arm.cc
Index: src/arm/assembler-arm.h
diff --git a/src/arm/assembler-arm.h b/src/arm/assembler-arm.h
index
49881cfd0d2ffb24f8421d54b1a71dbfce390ae2..727b0542115325f1d4eb6b395bb6e838cca9affd
100644
--- a/src/arm/assembler-arm.h
+++ b/src/arm/assembler-arm.h
@@ -379,8 +379,9 @@ struct QwNeonRegister {
}
void split_code(int* vm, int* m) const {
ASSERT(is_valid());
- *m = (code_ & 0x10) >> 4;
- *vm = code_ & 0x0F;
+ int encoded_code = code_ << 1;
+ *m = (encoded_code & 0x10) >> 4;
+ *vm = encoded_code & 0x0F;
}
int code_;
Index: src/arm/constants-arm.h
diff --git a/src/arm/constants-arm.h b/src/arm/constants-arm.h
index
78bb66c49fe315cbda1e10bd1a9aa6f8f2e0ad38..14f4705cbdf5e63edf2e786dd5f747382f1cb4b5
100644
--- a/src/arm/constants-arm.h
+++ b/src/arm/constants-arm.h
@@ -343,7 +343,7 @@ enum NeonSize {
Neon8 = 0x0,
Neon16 = 0x1,
Neon32 = 0x2,
- Neon64 = 0x4
+ Neon64 = 0x3
};
//
-----------------------------------------------------------------------------
Index: src/arm/disasm-arm.cc
diff --git a/src/arm/disasm-arm.cc b/src/arm/disasm-arm.cc
index
49e4126b32685d8329ed5fbe4b16f1103b92d192..0d9f7ec9b14e4f0f69b9a986cacd9e7e9fea8c49
100644
--- a/src/arm/disasm-arm.cc
+++ b/src/arm/disasm-arm.cc
@@ -1566,7 +1566,8 @@ void Decoder::DecodeSpecialCondition(Instruction*
instr) {
if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) &&
(instr->Bit(4) == 1)) {
// vmovl signed
- int Vd = (instr->Bit(22) << 4) | instr->VdValue();
+ if ((instr->VdValue() & 1) != 0) Unknown(instr);
+ int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1);
int Vm = (instr->Bit(5) << 4) | instr->VmValue();
int imm3 = instr->Bits(21, 19);
out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
@@ -1579,7 +1580,8 @@ void Decoder::DecodeSpecialCondition(Instruction*
instr) {
if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) &&
(instr->Bit(4) == 1)) {
// vmovl unsigned
- int Vd = (instr->Bit(22) << 4) | instr->VdValue();
+ if ((instr->VdValue() & 1) != 0) Unknown(instr);
+ int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1);
int Vm = (instr->Bit(5) << 4) | instr->VmValue();
int imm3 = instr->Bits(21, 19);
out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
Index: src/arm/simulator-arm.cc
diff --git a/src/arm/simulator-arm.cc b/src/arm/simulator-arm.cc
index
a7fccddc96b63b085d3ad7a228c5ef4ae381b483..8f7c1e8bb2b740e7884c6ae52c6b867681c9e125
100644
--- a/src/arm/simulator-arm.cc
+++ b/src/arm/simulator-arm.cc
@@ -3470,7 +3470,8 @@ void Simulator::DecodeSpecialCondition(Instruction*
instr) {
if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) &&
(instr->Bit(4) == 1)) {
// vmovl signed
- int Vd = (instr->Bit(22) << 4) | instr->VdValue();
+ if ((instr->VdValue() & 1) != 0) UNIMPLEMENTED();
+ int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1);
int Vm = (instr->Bit(5) << 4) | instr->VmValue();
int imm3 = instr->Bits(21, 19);
if ((imm3 != 1) && (imm3 != 2) && (imm3 != 4)) UNIMPLEMENTED();
@@ -3493,7 +3494,8 @@ void Simulator::DecodeSpecialCondition(Instruction*
instr) {
if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) &&
(instr->Bit(4) == 1)) {
// vmovl unsigned
- int Vd = (instr->Bit(22) << 4) | instr->VdValue();
+ if ((instr->VdValue() & 1) != 0) UNIMPLEMENTED();
+ int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1);
int Vm = (instr->Bit(5) << 4) | instr->VmValue();
int imm3 = instr->Bits(21, 19);
if ((imm3 != 1) && (imm3 != 2) && (imm3 != 4)) UNIMPLEMENTED();
Index: test/cctest/test-assembler-arm.cc
diff --git a/test/cctest/test-assembler-arm.cc
b/test/cctest/test-assembler-arm.cc
index
b21dc34dc4afcebb0a9d3293e1ea2f50bbee8b4b..9c1c04fe338f52ad478bd61ec306736c5c39ed46
100644
--- a/test/cctest/test-assembler-arm.cc
+++ b/test/cctest/test-assembler-arm.cc
@@ -1266,6 +1266,10 @@ TEST(15) {
uint32_t dstA1;
uint32_t dstA2;
uint32_t dstA3;
+ uint32_t dstA4;
+ uint32_t dstA5;
+ uint32_t dstA6;
+ uint32_t dstA7;
} T;
T t;
@@ -1291,7 +1295,14 @@ TEST(15) {
__ add(r4, r0, Operand(OFFSET_OF(T, dstA0)));
__ vst1(Neon8, NeonListOperand(d0, 2), NeonMemOperand(r4));
- __ ldm(ia_w, sp, r4.bit() | pc.bit());
+ // The same expansion, but with different source and destination
registers.
+ __ add(r4, r0, Operand(OFFSET_OF(T, srcA0)));
+ __ vld1(Neon8, NeonListOperand(d1), NeonMemOperand(r4));
+ __ vmovl(NeonU8, q1, d1);
+ __ add(r4, r0, Operand(OFFSET_OF(T, dstA4)));
+ __ vst1(Neon8, NeonListOperand(d2, 2), NeonMemOperand(r4));
+
+ __ ldm(ia_w, sp, r4.bit() | pc.bit());
CodeDesc desc;
assm.GetCode(&desc);
@@ -1326,6 +1337,10 @@ TEST(15) {
t.dstA1 = 0;
t.dstA2 = 0;
t.dstA3 = 0;
+ t.dstA4 = 0;
+ t.dstA5 = 0;
+ t.dstA6 = 0;
+ t.dstA7 = 0;
Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0);
USE(dummy);
CHECK_EQ(0x01020304, t.dst0);
@@ -1340,6 +1355,10 @@ TEST(15) {
CHECK_EQ(0x00410042, t.dstA1);
CHECK_EQ(0x00830084, t.dstA2);
CHECK_EQ(0x00810082, t.dstA3);
+ CHECK_EQ(0x00430044, t.dstA4);
+ CHECK_EQ(0x00410042, t.dstA5);
+ CHECK_EQ(0x00830084, t.dstA6);
+ CHECK_EQ(0x00810082, t.dstA7);
}
}
Index: test/cctest/test-disasm-arm.cc
diff --git a/test/cctest/test-disasm-arm.cc b/test/cctest/test-disasm-arm.cc
index
56f093eff85cb1a8f6a2926eac147a5cc203dbc8..a5a2b2fbb2cc11d8e64729918069d88a1b3fc6cc
100644
--- a/test/cctest/test-disasm-arm.cc
+++ b/test/cctest/test-disasm-arm.cc
@@ -687,8 +687,10 @@ TEST(Neon) {
"f421420f vld1.8 {d4, d5, d6, d7}, [r1]");
COMPARE(vst1(Neon16, NeonListOperand(d17, 4), NeonMemOperand(r9)),
"f449124f vst1.16 {d17, d18, d19, d20}, [r9]");
+ COMPARE(vmovl(NeonU8, q3, d1),
+ "f3886a11 vmovl.u8 q3, d1");
COMPARE(vmovl(NeonU8, q4, d2),
- "f3884a12 vmovl.u8 q4, d2");
+ "f3888a12 vmovl.u8 q4, d2");
}
VERIFY_RUN();
--
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