Revision: 20163
Author: [email protected]
Date: Fri Mar 21 13:04:20 2014 UTC
Log: ARM: Fix Q register encoding
Fix Q register encoding for registers other than Q0. Also, fix value in
NeonSize
enumeration.
BUG=
[email protected]
Review URL: https://codereview.chromium.org/207523005
http://code.google.com/p/v8/source/detail?r=20163
Modified:
/branches/bleeding_edge/src/arm/assembler-arm.h
/branches/bleeding_edge/src/arm/constants-arm.h
/branches/bleeding_edge/src/arm/disasm-arm.cc
/branches/bleeding_edge/src/arm/simulator-arm.cc
/branches/bleeding_edge/test/cctest/test-assembler-arm.cc
/branches/bleeding_edge/test/cctest/test-disasm-arm.cc
=======================================
--- /branches/bleeding_edge/src/arm/assembler-arm.h Wed Mar 19 10:32:12
2014 UTC
+++ /branches/bleeding_edge/src/arm/assembler-arm.h Fri Mar 21 13:04:20
2014 UTC
@@ -379,8 +379,9 @@
}
void split_code(int* vm, int* m) const {
ASSERT(is_valid());
- *m = (code_ & 0x10) >> 4;
- *vm = code_ & 0x0F;
+ int encoded_code = code_ << 1;
+ *m = (encoded_code & 0x10) >> 4;
+ *vm = encoded_code & 0x0F;
}
int code_;
=======================================
--- /branches/bleeding_edge/src/arm/constants-arm.h Wed Nov 27 10:07:57
2013 UTC
+++ /branches/bleeding_edge/src/arm/constants-arm.h Fri Mar 21 13:04:20
2014 UTC
@@ -343,7 +343,7 @@
Neon8 = 0x0,
Neon16 = 0x1,
Neon32 = 0x2,
- Neon64 = 0x4
+ Neon64 = 0x3
};
//
-----------------------------------------------------------------------------
=======================================
--- /branches/bleeding_edge/src/arm/disasm-arm.cc Wed Nov 27 10:07:57 2013
UTC
+++ /branches/bleeding_edge/src/arm/disasm-arm.cc Fri Mar 21 13:04:20 2014
UTC
@@ -1566,7 +1566,8 @@
if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) &&
(instr->Bit(4) == 1)) {
// vmovl signed
- int Vd = (instr->Bit(22) << 4) | instr->VdValue();
+ if ((instr->VdValue() & 1) != 0) Unknown(instr);
+ int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1);
int Vm = (instr->Bit(5) << 4) | instr->VmValue();
int imm3 = instr->Bits(21, 19);
out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
@@ -1579,7 +1580,8 @@
if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) &&
(instr->Bit(4) == 1)) {
// vmovl unsigned
- int Vd = (instr->Bit(22) << 4) | instr->VdValue();
+ if ((instr->VdValue() & 1) != 0) Unknown(instr);
+ int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1);
int Vm = (instr->Bit(5) << 4) | instr->VmValue();
int imm3 = instr->Bits(21, 19);
out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
=======================================
--- /branches/bleeding_edge/src/arm/simulator-arm.cc Fri Feb 28 10:55:47
2014 UTC
+++ /branches/bleeding_edge/src/arm/simulator-arm.cc Fri Mar 21 13:04:20
2014 UTC
@@ -3470,7 +3470,8 @@
if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) &&
(instr->Bit(4) == 1)) {
// vmovl signed
- int Vd = (instr->Bit(22) << 4) | instr->VdValue();
+ if ((instr->VdValue() & 1) != 0) UNIMPLEMENTED();
+ int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1);
int Vm = (instr->Bit(5) << 4) | instr->VmValue();
int imm3 = instr->Bits(21, 19);
if ((imm3 != 1) && (imm3 != 2) && (imm3 != 4)) UNIMPLEMENTED();
@@ -3493,7 +3494,8 @@
if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) &&
(instr->Bit(4) == 1)) {
// vmovl unsigned
- int Vd = (instr->Bit(22) << 4) | instr->VdValue();
+ if ((instr->VdValue() & 1) != 0) UNIMPLEMENTED();
+ int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1);
int Vm = (instr->Bit(5) << 4) | instr->VmValue();
int imm3 = instr->Bits(21, 19);
if ((imm3 != 1) && (imm3 != 2) && (imm3 != 4)) UNIMPLEMENTED();
=======================================
--- /branches/bleeding_edge/test/cctest/test-assembler-arm.cc Thu Jan 2
16:36:21 2014 UTC
+++ /branches/bleeding_edge/test/cctest/test-assembler-arm.cc Fri Mar 21
13:04:20 2014 UTC
@@ -1266,6 +1266,10 @@
uint32_t dstA1;
uint32_t dstA2;
uint32_t dstA3;
+ uint32_t dstA4;
+ uint32_t dstA5;
+ uint32_t dstA6;
+ uint32_t dstA7;
} T;
T t;
@@ -1291,7 +1295,14 @@
__ add(r4, r0, Operand(OFFSET_OF(T, dstA0)));
__ vst1(Neon8, NeonListOperand(d0, 2), NeonMemOperand(r4));
- __ ldm(ia_w, sp, r4.bit() | pc.bit());
+ // The same expansion, but with different source and destination
registers.
+ __ add(r4, r0, Operand(OFFSET_OF(T, srcA0)));
+ __ vld1(Neon8, NeonListOperand(d1), NeonMemOperand(r4));
+ __ vmovl(NeonU8, q1, d1);
+ __ add(r4, r0, Operand(OFFSET_OF(T, dstA4)));
+ __ vst1(Neon8, NeonListOperand(d2, 2), NeonMemOperand(r4));
+
+ __ ldm(ia_w, sp, r4.bit() | pc.bit());
CodeDesc desc;
assm.GetCode(&desc);
@@ -1326,6 +1337,10 @@
t.dstA1 = 0;
t.dstA2 = 0;
t.dstA3 = 0;
+ t.dstA4 = 0;
+ t.dstA5 = 0;
+ t.dstA6 = 0;
+ t.dstA7 = 0;
Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0);
USE(dummy);
CHECK_EQ(0x01020304, t.dst0);
@@ -1340,6 +1355,10 @@
CHECK_EQ(0x00410042, t.dstA1);
CHECK_EQ(0x00830084, t.dstA2);
CHECK_EQ(0x00810082, t.dstA3);
+ CHECK_EQ(0x00430044, t.dstA4);
+ CHECK_EQ(0x00410042, t.dstA5);
+ CHECK_EQ(0x00830084, t.dstA6);
+ CHECK_EQ(0x00810082, t.dstA7);
}
}
=======================================
--- /branches/bleeding_edge/test/cctest/test-disasm-arm.cc Tue Mar 11
20:17:02 2014 UTC
+++ /branches/bleeding_edge/test/cctest/test-disasm-arm.cc Fri Mar 21
13:04:20 2014 UTC
@@ -687,8 +687,10 @@
"f421420f vld1.8 {d4, d5, d6, d7}, [r1]");
COMPARE(vst1(Neon16, NeonListOperand(d17, 4), NeonMemOperand(r9)),
"f449124f vst1.16 {d17, d18, d19, d20}, [r9]");
+ COMPARE(vmovl(NeonU8, q3, d1),
+ "f3886a11 vmovl.u8 q3, d1");
COMPARE(vmovl(NeonU8, q4, d2),
- "f3884a12 vmovl.u8 q4, d2");
+ "f3888a12 vmovl.u8 q4, d2");
}
VERIFY_RUN();
--
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