Reviewers: Sven Panne,
Description:
ARM64: Fix cache line size computation.
BUG=
Please review this at https://codereview.chromium.org/268673020/
SVN Base: https://v8.googlecode.com/svn/branches/bleeding_edge
Affected files (+3, -2 lines):
M src/arm64/cpu-arm64.cc
Index: src/arm64/cpu-arm64.cc
diff --git a/src/arm64/cpu-arm64.cc b/src/arm64/cpu-arm64.cc
index
4f69be9d274ee9625d3cbabf568bc2bed38862b4..325eb6efb0cf6ce7df614966fef28608a4b8ea7c
100644
--- a/src/arm64/cpu-arm64.cc
+++ b/src/arm64/cpu-arm64.cc
@@ -39,8 +39,9 @@ class CacheLineSizes {
private:
uint32_t ExtractCacheLineSize(int cache_line_size_shift) const {
- // The cache type register holds the size of the caches as a power of
two.
- return 1 << ((cache_type_register_ >> cache_line_size_shift) & 0xf);
+ // The cache type register holds the size of cache lines in words as a
+ // power of two.
+ return 4 << ((cache_type_register_ >> cache_line_size_shift) & 0xf);
}
uint32_t cache_type_register_;
--
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