Revision: 21459
Author: [email protected]
Date: Fri May 23 09:41:41 2014 UTC
Log: ARM64 simulator fix for EXTR
Fixes extract when imms = 0 because a left shift of 64 is not valid.
[email protected], [email protected]
Review URL: https://codereview.chromium.org/286193004
http://code.google.com/p/v8/source/detail?r=21459
Modified:
/branches/bleeding_edge/src/arm64/simulator-arm64.cc
/branches/bleeding_edge/test/cctest/test-assembler-arm64.cc
=======================================
--- /branches/bleeding_edge/src/arm64/simulator-arm64.cc Fri May 23
07:14:04 2014 UTC
+++ /branches/bleeding_edge/src/arm64/simulator-arm64.cc Fri May 23
09:41:41 2014 UTC
@@ -2103,10 +2103,12 @@
unsigned lsb = instr->ImmS();
unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSizeInBits
: kWRegSizeInBits;
- set_reg(reg_size,
- instr->Rd(),
- (static_cast<uint64_t>(reg(reg_size, instr->Rm())) >> lsb) |
- (reg(reg_size, instr->Rn()) << (reg_size - lsb)));
+ uint64_t result = reg(reg_size, instr->Rm());
+ if (lsb) {
+ result = (result >> lsb) | (reg(reg_size, instr->Rn()) << (reg_size -
lsb));
+ }
+
+ set_reg(reg_size, instr->Rd(), result);
}
=======================================
--- /branches/bleeding_edge/test/cctest/test-assembler-arm64.cc Fri May 16
12:09:42 2014 UTC
+++ /branches/bleeding_edge/test/cctest/test-assembler-arm64.cc Fri May 23
09:41:41 2014 UTC
@@ -4892,26 +4892,30 @@
__ Mov(x2, 0xfedcba9876543210L);
__ Extr(w10, w1, w2, 0);
- __ Extr(w11, w1, w2, 1);
- __ Extr(x12, x2, x1, 2);
+ __ Extr(x11, x1, x2, 0);
+ __ Extr(w12, w1, w2, 1);
+ __ Extr(x13, x2, x1, 2);
- __ Ror(w13, w1, 0);
- __ Ror(w14, w2, 17);
- __ Ror(w15, w1, 31);
- __ Ror(x18, x2, 1);
- __ Ror(x19, x1, 63);
+ __ Ror(w20, w1, 0);
+ __ Ror(x21, x1, 0);
+ __ Ror(w22, w2, 17);
+ __ Ror(w23, w1, 31);
+ __ Ror(x24, x2, 1);
+ __ Ror(x25, x1, 63);
END();
RUN();
ASSERT_EQUAL_64(0x76543210, x10);
- ASSERT_EQUAL_64(0xbb2a1908, x11);
- ASSERT_EQUAL_64(0x0048d159e26af37bUL, x12);
- ASSERT_EQUAL_64(0x89abcdef, x13);
- ASSERT_EQUAL_64(0x19083b2a, x14);
- ASSERT_EQUAL_64(0x13579bdf, x15);
- ASSERT_EQUAL_64(0x7f6e5d4c3b2a1908UL, x18);
- ASSERT_EQUAL_64(0x02468acf13579bdeUL, x19);
+ ASSERT_EQUAL_64(0xfedcba9876543210L, x11);
+ ASSERT_EQUAL_64(0xbb2a1908, x12);
+ ASSERT_EQUAL_64(0x0048d159e26af37bUL, x13);
+ ASSERT_EQUAL_64(0x89abcdef, x20);
+ ASSERT_EQUAL_64(0x0123456789abcdefL, x21);
+ ASSERT_EQUAL_64(0x19083b2a, x22);
+ ASSERT_EQUAL_64(0x13579bdf, x23);
+ ASSERT_EQUAL_64(0x7f6e5d4c3b2a1908UL, x24);
+ ASSERT_EQUAL_64(0x02468acf13579bdeUL, x25);
TEARDOWN();
}
--
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