Reviewers: Benedikt Meurer,
Description:
Emulate MLS on pre-ARMv6T2.
This should unbreak things on the Raspberry Pi.
LOG=y
Please review this at https://codereview.chromium.org/331803003/
SVN Base: https://v8.googlecode.com/svn/branches/bleeding_edge
Affected files (+26, -6 lines):
M src/arm/assembler-arm.cc
M src/arm/lithium-codegen-arm.cc
M src/arm/macro-assembler-arm.h
M src/arm/macro-assembler-arm.cc
M src/flag-definitions.h
M src/globals.h
Index: src/arm/assembler-arm.cc
diff --git a/src/arm/assembler-arm.cc b/src/arm/assembler-arm.cc
index
ca5aad3f69f37c6f6c7a46bec66660c28fe088c8..c00107947366964cdcc9ea21625551ec4e57d419
100644
--- a/src/arm/assembler-arm.cc
+++ b/src/arm/assembler-arm.cc
@@ -84,10 +84,11 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
supported_ |= 1u << ARMv7;
if (FLAG_enable_vfp3) supported_ |= 1u << VFP3;
if (FLAG_enable_neon) supported_ |= 1u << NEON | 1u << VFP32DREGS;
- if (FLAG_enable_sudiv) supported_ |= 1u << SUDIV;
+ if (FLAG_enable_sudiv) supported_ |= 1u << SUDIV;
if (FLAG_enable_movw_movt) supported_ |= 1u <<
MOVW_MOVT_IMMEDIATE_LOADS;
if (FLAG_enable_32dregs) supported_ |= 1u << VFP32DREGS;
}
+ if (FLAG_enable_mls) supported_ |= 1u << MLS;
if (FLAG_enable_unaligned_accesses) supported_ |= 1u <<
UNALIGNED_ACCESSES;
#else // __arm__
@@ -102,6 +103,7 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
if (FLAG_enable_neon && cpu.has_neon()) supported_ |= 1u << NEON;
if (FLAG_enable_sudiv && cpu.has_idiva()) supported_ |= 1u << SUDIV;
+ if (FLAG_enable_mls && cpu.has_thumbee()) supported_ |= 1u << MLS;
if (cpu.architecture() >= 7) {
if (FLAG_enable_armv7) supported_ |= 1u << ARMv7;
@@ -744,7 +746,7 @@ int Assembler::GetCmpImmediateRawImmediate(Instr instr)
{
// same position.
-int Assembler::target_at(int pos) {
+int Assembler::target_at(int pos) {
Instr instr = instr_at(pos);
if (is_uint24(instr)) {
// Emitted link to a label, not part of a branch.
@@ -1481,6 +1483,7 @@ void Assembler::mla(Register dst, Register src1,
Register src2, Register srcA,
void Assembler::mls(Register dst, Register src1, Register src2, Register
srcA,
Condition cond) {
ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc));
+ ASSERT(IsEnabled(MLS));
emit(cond | B22 | B21 | dst.code()*B16 | srcA.code()*B12 |
src2.code()*B8 | B7 | B4 | src1.code());
}
Index: src/arm/lithium-codegen-arm.cc
diff --git a/src/arm/lithium-codegen-arm.cc b/src/arm/lithium-codegen-arm.cc
index
249c22f77bf3176b3e23583f3c29f1c02c274681..e98fcf4c08768dbd38eb44618d0847f66133fd41
100644
--- a/src/arm/lithium-codegen-arm.cc
+++ b/src/arm/lithium-codegen-arm.cc
@@ -1215,7 +1215,7 @@ void LCodeGen::DoModI(LModI* instr) {
// mls r3, r3, r2, r1
__ sdiv(result_reg, left_reg, right_reg);
- __ mls(result_reg, result_reg, right_reg, left_reg);
+ __ Mls(result_reg, result_reg, right_reg, left_reg);
// If we care about -0, test if the dividend is <0 and the result is 0.
if (hmod->CheckFlag(HValue::kBailoutOnMinusZero)) {
@@ -1413,7 +1413,7 @@ void LCodeGen::DoDivI(LDivI* instr) {
if (!hdiv->CheckFlag(HValue::kAllUsesTruncatingToInt32)) {
// Compute remainder and deopt if it's not zero.
Register remainder = scratch0();
- __ mls(remainder, result, divisor, dividend);
+ __ Mls(remainder, result, divisor, dividend);
__ cmp(remainder, Operand::Zero());
DeoptimizeIf(ne, instr->environment());
}
@@ -1588,7 +1588,7 @@ void LCodeGen::DoFlooringDivI(LFlooringDivI* instr) {
Label done;
Register remainder = scratch0();
- __ mls(remainder, result, right, left);
+ __ Mls(remainder, result, right, left);
__ cmp(remainder, Operand::Zero());
__ b(eq, &done);
__ eor(remainder, remainder, Operand(right));
Index: src/arm/macro-assembler-arm.cc
diff --git a/src/arm/macro-assembler-arm.cc b/src/arm/macro-assembler-arm.cc
index
a8d4b7ccd458d2e26ec54ee5c40ff3f1a51d0d20..c34a7f75b688f9e8a9ed5c2cf0aa742680d1253f
100644
--- a/src/arm/macro-assembler-arm.cc
+++ b/src/arm/macro-assembler-arm.cc
@@ -254,6 +254,19 @@ void MacroAssembler::Move(DwVfpRegister dst,
DwVfpRegister src) {
}
+void MacroAssembler::Mls(Register dst, Register src1, Register src2,
+ Register srcA, Condition cond) {
+ if (CpuFeatures::IsSupported(MLS)) {
+ CpuFeatureScope scope(this, MLS);
+ mls(dst, src1, src2, srcA, cond);
+ } else {
+ ASSERT(!dst.is(srcA));
+ mul(ip, src1, src2, LeaveCC, cond);
+ sub(dst, srcA, ip, LeaveCC, cond);
+ }
+}
+
+
void MacroAssembler::And(Register dst, Register src1, const Operand& src2,
Condition cond) {
if (!src2.is_reg() &&
Index: src/arm/macro-assembler-arm.h
diff --git a/src/arm/macro-assembler-arm.h b/src/arm/macro-assembler-arm.h
index
928995abbf6d63601d53ba469a640a4790b5791f..dbf305a4077c236303bd26781cc591d7088f3f86
100644
--- a/src/arm/macro-assembler-arm.h
+++ b/src/arm/macro-assembler-arm.h
@@ -117,7 +117,8 @@ class MacroAssembler: public Assembler {
Register scratch = no_reg,
Condition cond = al);
-
+ void Mls(Register dst, Register src1, Register src2, Register srcA,
+ Condition cond = al);
void And(Register dst, Register src1, const Operand& src2,
Condition cond = al);
void Ubfx(Register dst, Register src, int lsb, int width,
Index: src/flag-definitions.h
diff --git a/src/flag-definitions.h b/src/flag-definitions.h
index
f36a577f6ae1a1ac30ad60bd68d5e67f8dbc1f4d..1d83481f9e4c1b196a381e0db1b75d5e97019abd
100644
--- a/src/flag-definitions.h
+++ b/src/flag-definitions.h
@@ -373,6 +373,8 @@ DEFINE_bool(enable_neon, ENABLE_NEON_DEFAULT,
"enable use of NEON instructions if available (ARM only)")
DEFINE_bool(enable_sudiv, true,
"enable use of SDIV and UDIV instructions if available (ARM
only)")
+DEFINE_bool(enable_mls, true,
+ "enable use of MLS instructions if available (ARM only)")
DEFINE_bool(enable_movw_movt, false,
"enable loading 32-bit constant by means of movw/movt "
"instruction pairs (ARM only)")
Index: src/globals.h
diff --git a/src/globals.h b/src/globals.h
index
0c24c6e59dea386a4fbbd82f1fccf6315e0d69a4..8ac3840b81cf28466adf8e56591c29cf43b5aae2
100644
--- a/src/globals.h
+++ b/src/globals.h
@@ -616,6 +616,7 @@ enum CpuFeature {
VFP3,
ARMv7,
SUDIV,
+ MLS,
UNALIGNED_ACCESSES,
MOVW_MOVT_IMMEDIATE_LOADS,
VFP32DREGS,
--
--
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