Reviewers: ulan, jochen traveling until Jun 23, Benedikt Meurer,
Description:
ARM: Clean up FlushICache.
In theory, the Thumb version of FlushICache doesn't have to be any
different from the ARM version: There is no need to switch to ARM mode
for the svc, and r7 can be used just like any other register.
In practice, GCC uses r7 as a frame pointer in Thumb code, and it
refuses to allow it be used in inline assembly. To avoid complicated
preprocesor-based checks, the FlushICache function is declared 'naked'
and implemented in assembly.
BUG=
Please review this at https://codereview.chromium.org/335133002/
SVN Base: https://v8.googlecode.com/svn/branches/bleeding_edge
Affected files (+36, -46 lines):
M src/arm/cpu-arm.cc
Index: src/arm/cpu-arm.cc
diff --git a/src/arm/cpu-arm.cc b/src/arm/cpu-arm.cc
index
4ff82a78d4287e1ad3cb5d24bf339377d21e824d..1cee2db800876ba3de144e2118338079f6f30c1b
100644
--- a/src/arm/cpu-arm.cc
+++ b/src/arm/cpu-arm.cc
@@ -23,63 +23,53 @@
namespace v8 {
namespace internal {
-void CPU::FlushICache(void* start, size_t size) {
- // Nothing to do flushing no instructions.
- if (size == 0) {
- return;
- }
-
#if defined(USE_SIMULATOR)
+
+void CPU::FlushICache(void* start, size_t size) {
+ if (size == 0) return;
// Not generating ARM instructions for C-code. This means that we are
// building an ARM emulator based target. We should notify the simulator
// that the Icache was flushed.
// None of this code ends up in the snapshot so there are no issues
// around whether or not to generate the code when building snapshots.
Simulator::FlushICache(Isolate::Current()->simulator_i_cache(), start,
size);
+}
+
#elif V8_OS_QNX
- msync(start, size, MS_SYNC | MS_INVALIDATE_ICACHE);
+
+void CPU::FlushICache(void* start, size_t size) {
+ if (size > 0) msync(start, size, MS_SYNC | MS_INVALIDATE_ICACHE);
+}
+
#else
- // Ideally, we would call
- // syscall(__ARM_NR_cacheflush, start,
- // reinterpret_cast<intptr_t>(start) + size, 0);
- // however, syscall(int, ...) is not supported on all platforms,
especially
- // not when using EABI, so we call the __ARM_NR_cacheflush syscall
directly.
-
- register uint32_t beg asm("a1") = reinterpret_cast<uint32_t>(start);
- register uint32_t end asm("a2") =
- reinterpret_cast<uint32_t>(start) + size;
- register uint32_t flg asm("a3") = 0;
- #if defined (__arm__) && !defined(__thumb__)
- // __arm__ may be defined in thumb mode.
- register uint32_t scno asm("r7") = __ARM_NR_cacheflush;
- asm volatile(
- "svc 0x0"
- : "=r" (beg)
- : "0" (beg), "r" (end), "r" (flg), "r" (scno));
- #else
- // r7 is reserved by the EABI in thumb mode.
- asm volatile(
- "@ Enter ARM Mode \n\t"
- "adr r3, 1f \n\t"
- "bx r3 \n\t"
- ".ALIGN 4 \n\t"
- ".ARM \n"
- "1: push {r7} \n\t"
- "mov r7, %4 \n\t"
- "svc 0x0 \n\t"
- "pop {r7} \n\t"
- "@ Enter THUMB Mode\n\t"
- "adr r3, 2f+1 \n\t"
- "bx r3 \n\t"
- ".THUMB \n"
- "2: \n\t"
- : "=r" (beg)
- : "0" (beg), "r" (end), "r" (flg), "r" (__ARM_NR_cacheflush)
- : "r3");
- #endif
-#endif
+
+void __attribute__((naked)) CPU::FlushICache(void* start, size_t size) {
+ // On entry:
+ // r0 = start
+ // r1 = size
+ asm volatile(
+ // This assembly works for both ARM and Thumb targets.
+
+ // Preserve r7, since it is callee-saved.
+ " push {r7, lr}\n"
+
+ // Perform the syscall (if size > 0).
+ " cmp r1, #0\n"
+ " beq 0f\n"
+ // r0 = start
+ " adds r1, r1, r0\n" // r1 = end (= start + size)
+ " movs r2, #0\n" // r2 = flags (= 0)
+ " ldr r7, =%[scno]\n" // r7 = syscall number.
+ " svc 0\n"
+
+ // Restore r7 and return.
+ "0:\n"
+ " pop {r7, pc}\n"
+ : : [scno] "i" (__ARM_NR_cacheflush) : "memory", "cc");
}
+#endif
+
} } // namespace v8::internal
#endif // V8_TARGET_ARCH_ARM
--
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