Revision: 21928
Author: [email protected]
Date: Mon Jun 23 10:31:12 2014 UTC
Log: Revert "Partial revert of r21901"
This reverts r21927.
Reason: broke the build.
BUG=
[email protected], [email protected]
Review URL: https://codereview.chromium.org/347423002
http://code.google.com/p/v8/source/detail?r=21928
Modified:
/branches/bleeding_edge/src/base/atomicops_internals_x86_gcc.cc
/branches/bleeding_edge/src/base/atomicops_internals_x86_gcc.h
=======================================
--- /branches/bleeding_edge/src/base/atomicops_internals_x86_gcc.cc Mon Jun
23 10:18:43 2014 UTC
+++ /branches/bleeding_edge/src/base/atomicops_internals_x86_gcc.cc Mon Jun
23 10:31:12 2014 UTC
@@ -42,7 +42,6 @@
// default values should hopefully be pretty safe.
struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = {
false, // bug can't exist before process spawns multiple threads
- false, // no SSE2
};
} } // namespace v8::base
@@ -88,11 +87,6 @@
} else {
AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false;
}
-
-#if !defined(__SSE2__)
- // edx bit 26 is SSE2 which we use to tell use whether we can use mfence
- AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1);
-#endif
}
class AtomicOpsx86Initializer {
=======================================
--- /branches/bleeding_edge/src/base/atomicops_internals_x86_gcc.h Mon Jun
23 10:18:43 2014 UTC
+++ /branches/bleeding_edge/src/base/atomicops_internals_x86_gcc.h Mon Jun
23 10:31:12 2014 UTC
@@ -17,9 +17,6 @@
struct AtomicOps_x86CPUFeatureStruct {
bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do
lfence
// after acquire compare-and-swap.
-#if !defined(__SSE2__)
- bool has_sse2; // Processor has SSE2.
-#endif
};
extern struct AtomicOps_x86CPUFeatureStruct
AtomicOps_Internalx86CPUFeatures;
@@ -94,10 +91,7 @@
*ptr = value;
}
-#if defined(__x86_64__) || defined(__SSE2__)
-
-// 64-bit implementations of memory barrier can be simpler, because it
-// "mfence" is guaranteed to exist.
+// We require SSE2, so mfence is guaranteed to exist.
inline void MemoryBarrier() {
__asm__ __volatile__("mfence" : : : "memory");
}
@@ -106,28 +100,6 @@
*ptr = value;
MemoryBarrier();
}
-
-#else
-
-inline void MemoryBarrier() {
- if (AtomicOps_Internalx86CPUFeatures.has_sse2) {
- __asm__ __volatile__("mfence" : : : "memory");
- } else { // mfence is faster but not present on PIII
- Atomic32 x = 0;
- NoBarrier_AtomicExchange(&x, 0); // acts as a barrier on PIII
- }
-}
-
-inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
- if (AtomicOps_Internalx86CPUFeatures.has_sse2) {
- *ptr = value;
- __asm__ __volatile__("mfence" : : : "memory");
- } else {
- NoBarrier_AtomicExchange(ptr, value);
- // acts as a barrier on PIII
- }
-}
-#endif
inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
ATOMICOPS_COMPILER_BARRIER();
--
--
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