Author: sewardj
Date: 2007-09-26 23:43:10 +0100 (Wed, 26 Sep 2007)
New Revision: 1790
Log:
XCHG reg,mem automatically asserts LOCK# even without a LOCK prefix --
handle it correctly.
Modified:
branches/THRCHECK/priv/guest-amd64/toIR.c
branches/THRCHECK/priv/guest-x86/toIR.c
Modified: branches/THRCHECK/priv/guest-amd64/toIR.c
===================================================================
--- branches/THRCHECK/priv/guest-amd64/toIR.c 2007-09-16 11:04:24 UTC (rev
1789)
+++ branches/THRCHECK/priv/guest-amd64/toIR.c 2007-09-26 22:43:10 UTC (rev
1790)
@@ -13727,6 +13727,12 @@
/* ------------------------ XCHG ----------------------- */
+ /* XCHG reg,mem automatically asserts LOCK# even without a LOCK
+ prefix. Therefore, surround it with a IRStmt_MBE(Imbe_BusLock)
+ and IRStmt_MBE(Imbe_BusUnlock) pair. But be careful; if it is
+ used with an explicit LOCK prefix, we don't want to end up with
+ two IRStmt_MBE(Imbe_BusLock)s -- one made here and one made by
+ the generic LOCK logic at the top of disInstr. */
case 0x86: /* XCHG Gb,Eb */
sz = 1;
/* Fall through ... */
@@ -13745,6 +13751,18 @@
nameISize(sz), nameIRegG(sz, pfx, modrm),
nameIRegE(sz, pfx, modrm));
} else {
+ /* Need to add IRStmt_MBE(Imbe_BusLock). */
+ if (pfx & PFX_LOCK) {
+ /* check it's already been taken care of */
+ vassert(unlock_bus_after_insn);
+ } else {
+ vassert(!unlock_bus_after_insn);
+ stmt( IRStmt_MBE(Imbe_BusLock) );
+ unlock_bus_after_insn = True;
+ }
+ /* Because unlock_bus_after_insn is now True, generic logic
+ at the bottom of disInstr will add the
+ IRStmt_MBE(Imbe_BusUnlock). */
addr = disAMode ( &alen, pfx, delta, dis_buf, 0 );
assign( t1, loadLE(ty, mkexpr(addr)) );
assign( t2, getIRegG(sz, pfx, modrm) );
Modified: branches/THRCHECK/priv/guest-x86/toIR.c
===================================================================
--- branches/THRCHECK/priv/guest-x86/toIR.c 2007-09-16 11:04:24 UTC (rev
1789)
+++ branches/THRCHECK/priv/guest-x86/toIR.c 2007-09-26 22:43:10 UTC (rev
1790)
@@ -12306,6 +12306,12 @@
/* ------------------------ XCHG ----------------------- */
+ /* XCHG reg,mem automatically asserts LOCK# even without a LOCK
+ prefix. Therefore, surround it with a IRStmt_MBE(Imbe_BusLock)
+ and IRStmt_MBE(Imbe_BusUnlock) pair. But be careful; if it is
+ used with an explicit LOCK prefix, we don't want to end up with
+ two IRStmt_MBE(Imbe_BusLock)s -- one made here and one made by
+ the generic LOCK logic at the top of disInstr. */
case 0x86: /* XCHG Gb,Eb */
sz = 1;
/* Fall through ... */
@@ -12323,6 +12329,18 @@
nameISize(sz), nameIReg(sz,gregOfRM(modrm)),
nameIReg(sz,eregOfRM(modrm)));
} else {
+ /* Need to add IRStmt_MBE(Imbe_BusLock). */
+ if (pfx_lock) {
+ /* check it's already been taken care of */
+ vassert(unlock_bus_after_insn);
+ } else {
+ vassert(!unlock_bus_after_insn);
+ stmt( IRStmt_MBE(Imbe_BusLock) );
+ unlock_bus_after_insn = True;
+ }
+ /* Because unlock_bus_after_insn is now True, generic logic
+ at the bottom of disInstr will add the
+ IRStmt_MBE(Imbe_BusUnlock). */
addr = disAMode ( &alen, sorb, delta, dis_buf );
assign( t1, loadLE(ty,mkexpr(addr)) );
assign( t2, getIReg(sz,gregOfRM(modrm)) );
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