Author: bart
Date: 2008-03-07 17:22:26 +0000 (Fri, 07 Mar 2008)
New Revision: 7581
Log:
Added support for atomic modifications (VEX' Imbe_BusLock/Imbe_BusUnlock).
Modified:
trunk/exp-drd/drd_main.c
trunk/exp-drd/tests/tc11_XCHG.stderr.exp
Modified: trunk/exp-drd/drd_main.c
===================================================================
--- trunk/exp-drd/drd_main.c 2008-03-06 21:56:18 UTC (rev 7580)
+++ trunk/exp-drd/drd_main.c 2008-03-07 17:22:26 UTC (rev 7581)
@@ -54,15 +54,10 @@
// Function declarations.
-static void instrument_memory_bus_event(IRSB* const bb,
- const IRMBusEvent event);
static void drd_start_client_code(const ThreadId tid, const ULong bbs_done);
static void drd_set_running_tid(const ThreadId tid);
-static void evh__bus_lock(void);
-static void evh__bus_unlock(void);
-
// Local variables.
static Bool drd_print_stats = False;
@@ -583,6 +578,7 @@
IRExpr* addr_expr;
IRExpr* size_expr;
Bool instrument = True;
+ Bool bus_locked = False;
/* Set up BB */
bb = emptyIRSB();
@@ -605,12 +601,26 @@
break;
case Ist_MBE:
- instrument_memory_bus_event(bb, st->Ist.MBE.event);
+ switch (st->Ist.MBE.event)
+ {
+ case Imbe_Fence:
+ break; /* not interesting */
+ case Imbe_BusLock:
+ tl_assert(! bus_locked);
+ bus_locked = True;
+ break;
+ case Imbe_BusUnlock:
+ tl_assert(bus_locked);
+ bus_locked = False;
+ break;
+ default:
+ tl_assert(0);
+ }
addStmtToIRSB(bb, st);
break;
case Ist_Store:
- if (instrument)
+ if (instrument && ! bus_locked)
{
addr_expr = st->Ist.Store.addr;
size_expr = mkIRExpr_HWord(
@@ -666,7 +676,9 @@
argv);
addStmtToIRSB(bb, IRStmt_Dirty(di));
}
- if (mFx == Ifx_Write || mFx == Ifx_Modify) {
+ if ((mFx == Ifx_Write || mFx == Ifx_Modify)
+ && ! bus_locked)
+ {
di = unsafeIRDirty_0_N(
/*regparms*/2,
"drd_trace_store",
@@ -688,50 +700,11 @@
}
}
+ tl_assert(! bus_locked);
+
return bb;
}
-/* Based on the function with the same name in Helgrind's hg_main.c */
-static void instrument_memory_bus_event(IRSB* const bb,
- const IRMBusEvent event)
-{
- switch (event)
- {
- case Imbe_Fence:
- break; /* not interesting */
- case Imbe_BusLock:
- addStmtToIRSB(bb,
- IRStmt_Dirty(unsafeIRDirty_0_N(0/*regparms*/, "evh__bus_lock",
- VG_(fnptr_to_fnentry)(&evh__bus_lock), mkIRExprVec_0())
- ));
- break;
- case Imbe_BusUnlock:
- addStmtToIRSB(bb,
- IRStmt_Dirty(unsafeIRDirty_0_N(0/*regparms*/, "evh__bus_unlock",
- VG_(fnptr_to_fnentry)(&evh__bus_unlock), mkIRExprVec_0())
- ));
- break;
- default:
- tl_assert(0);
- }
-}
-
-/** Locking the memory bus is a way to serialize store operations.
- * What the lwarx / stwcx instructions do on PowerPC is to detect whether
- * any other CPU has invalidated the cache line in which the location
- * specified by lwarx resides has been invalidated at the time the stwcx
- * instruction is executed.
- */
-static void evh__bus_lock(void)
-{
- /* To do: implement this function. */
-}
-
-static void evh__bus_unlock(void)
-{
- /* To do: implement this function. */
-}
-
static void drd_set_running_tid(const ThreadId vg_tid)
{
static ThreadId s_last_vg_tid = VG_INVALID_THREADID;
Modified: trunk/exp-drd/tests/tc11_XCHG.stderr.exp
===================================================================
--- trunk/exp-drd/tests/tc11_XCHG.stderr.exp 2008-03-06 21:56:18 UTC (rev
7580)
+++ trunk/exp-drd/tests/tc11_XCHG.stderr.exp 2008-03-07 17:22:26 UTC (rev
7581)
@@ -1,18 +1,3 @@
-Conflicting load by thread 1 at 0x........ size 4
- at 0x........: main (tc11_XCHG.c:78)
-Allocation context: unknown
-Other segment start (thread 2)
- (thread finished, call stack no longer available)
-Other segment end (thread 2)
- (thread finished, call stack no longer available)
-Conflicting store by thread 1 at 0x........ size 4
- at 0x........: main (tc11_XCHG.c:78)
-Allocation context: unknown
-Other segment start (thread 2)
- (thread finished, call stack no longer available)
-Other segment end (thread 2)
- (thread finished, call stack no longer available)
-
-ERROR SUMMARY: 2 errors from 2 contexts (suppressed: 0 from 0)
+ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
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