Hi,
This is quite an old topic, but I get exact the same problem. With
objdump -M e500x2, I think below is the "real" instruction
be6c: 94 21 fd 50 stwu r1,-688(r1)
be70: 7c 08 02 a6 mflr r0
be74: 39 c0 02 98 li r14,664
be78: 48 01 c1 89 bl 28000 <__libc_enable_secure+0xbc>
be7c: 13 c1 73 20 evstddx r30,r1,r14
be80: 39 c0 02 a0 li r14,672
be84: 7f c8 02 a6 mflr r30
be88: 13 e1 73 20 evstddx r31,r1,r14
Accoring to PowerISA and EREF, evstddx is an SPE APU. As I'm not
familiar with valgrind implementation, could you give me some info about
how to support these SPE APU extentions? One of them, of course, would
be decoding. :)
Jaguar
Julian Seward Wrote:
> Hi. I did look into this problem a few months back. The difficulty is that
> supporting e500 is a lot more complex than merely making the isel instruction
> work. Once isel is fixed, you then run into this, as you observed
>
>> Output of objdump -d ld-2.3.3.so file where the error has been shown
>> (vmhaddshs - I guess so).
>>
>> 0000c254 <_dl_catch_error>:
>> c254: 94 21 fd 50 stwu r1,-688(r1)
>> c258: 7c 08 02 a6 mflr r0
>> c25c: 39 c0 02 98 li r14,664
>> c260: 48 01 bd a1 bl 28000 <_DYNAMIC+0xbc>
>> c264: 13 c1 73 20 vmhaddshs v30,v1,v14,v12
>> c268: 39 c0 02 a0 li r14,672
>> c26c: 7f c8 02 a6 mflr r30
>> c270: 13 e1 73 20 vmhaddshs v31,v1,v14,v12
>
> These appear to be e500 specific instructions which occupy the same decoding
> space as Altivec (vmhaddshs is an Altivec instruction, and it is complete
> nonsense for it to appear in this context).
>
> So fixing e500 support properly would require both adding support for some
> unknown number of new instructions, and also messing with the cpu capabilities
> stuff so as to know whether to decode such instructions as Altivec or e500
> extensions. And, lacking access to any real e500 hardware, at that point
> my investigation simply stopped.
>
> J
>
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