> vex amd64->IR: unhandled instruction bytes: 0xC0 0x36 0x7D 0x5A 0x0 0x0
The instruction bytes "C0 36" are officially undefined. The second byte
("modR/M" in the Intel nomenclature) 0x36 designates case 6==(0x7 & (0x36 >> 3))
which would be an 8-bit shift (SHL) with immediate constant shift count,
except that SHL and SAL are equivalent, so the case 4 is used for both,
and case 6 is undefined. The code generator forgot this special tweak.
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