> [M Rajesh-B22236] Here is /proc/cpuinfo values
> processor       : 0
> cpu             : e500v2
> clock           : 1499.985015MHz
> revision        : 3.0 (pvr 8021 0030)
> bogomips        : 149.50
> 
> total bogomips  : 149.50
> timebase        : 74999251
> platform        : MPC8572 DS
> model           : fsl,MPC8572DS

>> disInstr(ppc): unhandled instruction: 0x10E40301
>>
>>                  primary 4(0x4), secondary 769(0x301)

> [jreiser] That instruction seems to be:
>       evldd   r7,0(r4)
> 
> which is an instruction for SPE (Signal Processing Engine):
>    evldd[x]         Vector Load Double Word into Double Word [Indexed]
> 
> which is described on pdf page 513 of:
>    http://www.st.com/stonline/products/literature/rm/13694.pdf
>    Programmer's reference manual for Book E processors
>    Book E, a version of the PowerPC architecture intended for embedded 
> processors

Valgrind source code VEX/priv/guest_ppc_toIR.c seems to recognize none of the 
SPE
nor APU (Auxiliary Processing Unit) instructions.  Looking carefully at Book E,
it seems that a "32-bit CPU" that has SPE and APU must have 64-bit General
Purpose Registers, and that the data layout is full of endian problems.

The application file name "pspmaster" hints at an association with
a well-known consumer electronics company.  If true, then they should
spend some money to implement the extensions required for VEX and valgrind.

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