Am 07.12.2012 20:46, schrieb Jason Palaszewski:
> Hi, I'm trying to compare the number of cache misses (D1, I1, and LL)
> between what Perf gives me (on the hardware itself) vs. what
> Cachegrind thinks the number of misses should be. The server machine
> has two Sandy Bridge Intel Xeon E5-2430 CPUs on it, and the PARSEC 3.0
> suite (compiled in gcc-serial format, single threaded) is being run
> through cachegrind for analysis to obtain the number of D1, I1, and LL
> misses vs. the number of real misses on the hardware obtained by
> running the same benchmark binaries through Perf and counting D1 load
> and store misses as well as I1 misses. A ratio of the Perf misses to
> Cachegrind misses holds to about a factor of 1-2x. However, some
> benchmarks like ferret have a much higher number of misses on Perf
> than on Cachegrind.

Is this LL misses, or L1 misses? For L1 misses, you may observe much
more misses as real caches are asynchronous, ie. consecutive loads to
the same line will give as much misses as loads, while in Cachegrind
after the first miss all others will be hits.

Hm. Is ferret pure user-space, or does it trigger work in the kernel?
It may be that the kernel side evicts a lot of data from the cache,
and this becomes visible via user-level cache misses.

Another possibility is that hardware prefetching is too clever, and
evicts lines to enable prefetching of data which is not actually used.

Josef

  Has anyone else done analysis on Perf results vs.
> Cachegrind simulated results by running benchmarks on both of these?
> The machines are also running RedHat 5. Thanks for any information.
>
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