Hi,

I'm new to the list. A quick look at the archives found a number of people 
asking and not much clear guidance. If there is a document or thread that I 
need to look at, could you please point the way?

I have a critical need to understand the cache use and memory access for a 
circuit simulation situation. We are doing circuit simulation and need to run 
months of simulation for a particular project. I am the person tasked with 
building up the compute platform for this and I am trying to decide how to 
balance processor speed, cache size and cost to get the most simulation runs 
for our budget. The number of sims is near infinite, so it really about getting 
the most done for the buck.

As an added twist, one of the apps is a vendor supplied 32 bit app so I have 
needed to get 32 bit apps and libraries on my 64 bit machine to get cachegrind 
to run.

One of my test platforms that I build for another project has a pair of Intel 
Xeon e5-2643v2 processors. These have 6 cores and 25MB of L3 cache, so it gives 
me a great test for a high cache per core case. When I run cachegrind with no 
options, I get the right numbers back on the amount of memory and line width 
(64). I am guessing the number of associations (20) is right but I don't have 
specs to compare to.

Why is it insisting that the numbers be powers of 2? If I use --LL with the 
real numbers it refuses to start. If I round these down to the next lower power 
of 2 (16M and 16 associations) it doesn't complain but it still doesn't run.

What do I have to do to get this to work for me? What is the general solution 
for all the modern chips that have nothing bound to powers of 2? This seems to 
be a fundamental issue with modern processors.

thanks in advance,
jerry

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