I've pushed changes to fix these issues. Martin
On Mon, 8 Aug 2016 at 10:24 Poul-Henning Kamp <[email protected]> wrote: > They both look serious-ish... > > 2 new defect(s) introduced to varnish found with Coverity Scan. > > New defect(s) Reported-by: Coverity Scan Showing 2 of 2 defect(s) > > ** CID 1364600: Concurrent data access violations (MISSING_LOCK) /bin/ > varnishhist/varnishhist.c: 216 in upd_vsl_ts() > > > _____________________________________________________________________________________________________ > _ * CID 1364600: Concurrent data access violations (MISSING_LOCK) /bin/ > varnishhist/varnishhist.c: 216 in upd_vsl_ts() 210 if (p == NULL) 211 > return; > 212 213 t = strtod(p + 1, NULL); 214 215 if (t > vsl_ts) > > CID 1364600: Concurrent data access violations (MISSING_LOCK) > Accessing “vsl_ts” without holding lock “mtx”. Elsewhere, > “vsl_ts” > is accessed with “mtx” held 1 out of 2 times (1 of these > accesses > strongly imply that it is necessary). > > 216 vsl_ts = t; 217 } 218 219 static int /*__match_proto__ > (VSLQ_dispatch_f)*/ > 220 accumulate(struct VSL_data *vsl, struct VSL_transaction * const pt[], > 221 > void *priv) > > ** CID 1364599: Control flow issues (MISSING_BREAK) /bin/varnishhist/ > varnishhist.c: 271 in accumulate() > > > _____________________________________________________________________________________________________ > _ * CID 1364599: Control flow issues (MISSING_BREAK) /bin/varnishhist/ > varnishhist.c: 271 in accumulate() 265 > !strcasecmp(VSL_CDATA(tr->c->rec.ptr), > 266 "retry")) 267 skip = 1; 268 break; 269 case SLT_Timestamp: 270 tsp = > VSL_CDATA(tr->c->rec.ptr); > > CID 1364599: Control flow issues (MISSING_BREAK) The above case > falls through to this one. > > 271 default: 272 if (tag != match_tag) 273 break; 274 275 if > (active_profile-> > prefix && 276 strncmp(VSL_CDATA(tr->c->rec.ptr), > > > -- > Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 > [email protected] | TCP/IP since RFC 956 > FreeBSD committer | BSD since 4.3-tahoe > Never attribute to malice what can adequately be explained by incompetence. > > _______________________________________________ > varnish-dev mailing list > [email protected] > https://www.varnish-cache.org/lists/mailman/listinfo/varnish-dev
_______________________________________________ varnish-dev mailing list [email protected] https://www.varnish-cache.org/lists/mailman/listinfo/varnish-dev
