http://hg.viff.dk/viff/rev/ab726c059750
changeset: 1106:ab726c059750
user: Martin Geisler <[email protected]>
date: Fri Feb 20 10:20:34 2009 +0100
summary: More pyflakes "fixes".
diffstat:
2 files changed, 11 insertions(+), 12 deletions(-)
apps/benchmark.py | 6 ++++--
viff/test/test_util.py | 17 +++++++----------
diffs (74 lines):
diff -r 1d5f01ddd720 -r ab726c059750 apps/benchmark.py
--- a/apps/benchmark.py Fri Feb 20 10:00:48 2009 +0100
+++ b/apps/benchmark.py Fri Feb 20 10:20:34 2009 +0100
@@ -140,9 +140,11 @@
if options.fake:
print "Using fake field elements"
- GF = FakeGF
+ Field = FakeGF
+else:
+ Field = GF
-Zp = GF(find_prime(options.modulus))
+Zp = Field(find_prime(options.modulus))
print "Using field elements (%d bit modulus)" % log(Zp.modulus, 2)
count = options.count
diff -r 1d5f01ddd720 -r ab726c059750 viff/test/test_util.py
--- a/viff/test/test_util.py Fri Feb 20 10:00:48 2009 +0100
+++ b/viff/test/test_util.py Fri Feb 20 10:20:34 2009 +0100
@@ -21,8 +21,7 @@
from viff.util import deep_wait
from viff.field import GF, GF256
-import viff.shamir
-import viff.prss
+from viff import shamir, prss
from twisted.trial.unittest import TestCase
from twisted.internet.defer import Deferred
@@ -36,7 +35,7 @@
# Modules which will be reloaded with and without VIFF_FAKE set in
# the environment.
- _modules = [viff.shamir, viff.prss]
+ _modules = [shamir, prss]
def setUp(self):
self.field = GF(1031)
@@ -51,29 +50,27 @@
reload(module)
def test_shamir_share(self):
- from viff.shamir import share
secret = self.field(17)
- shares = share(secret, 1, 3)
+ shares = shamir.share(secret, 1, 3)
self.assertEquals(shares[0][1], secret)
self.assertEquals(shares[1][1], secret)
self.assertEquals(shares[2][1], secret)
def test_shamir_recombine(self):
- from viff.shamir import recombine
shares = [(1, 1), None, None]
- self.assertEquals(recombine(shares), 1)
+ self.assertEquals(shamir.recombine(shares), 1)
def test_prss(self):
- share = viff.prss.prss(None, None, self.field, None, None)
+ share = prss.prss(None, None, self.field, None, None)
self.assertEquals(share, self.field(7))
def test_prss_lsb(self):
- (share, bit) = viff.prss.prss_lsb(None, None, self.field, None, None)
+ (share, bit) = prss.prss_lsb(None, None, self.field, None, None)
self.assertEquals(share, self.field(7))
self.assertEquals(bit, GF256(1))
def test_prss_zero(self):
- share = viff.prss.prss_zero(None, None, None, self.field, None, None)
+ share = prss.prss_zero(None, None, None, self.field, None, None)
self.assertEquals(share, self.field(0))
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