Dear Mr. Meldgaard,
Thank you for your idea wich is very helpful to me since I actually work with p
Using this is much more efficient !
Le 9 avr. 2010 à 01:10, Sigurd Torkel Meldgaard a écrit :
> I know this is talking around the problem but:
> For very small moduli like yours, another protocol for equality is
> actually simpler, better (no risk of failing) and faster (I guess):
> raise (a-b) to n-1 (with square and multiply), and if this difference
> was 0 you will get 0, otherwise you will get 1 (good old fermat), this
> result can be subtracted from 1, to turn the bit correctly.
> I actually coded this once, but for some reason I never got to put it into
> I have attached a patch you can try to apply (use hg qimport
> fermatequality, hg qpush), and play with for now.
> I will try to look into the real bug later.
> The best
> On Thu, Apr 8, 2010 at 11:34 PM, Marcel Keller <mkel...@cs.au.dk> wrote:
>> Hi Jonathan,
>> I can't reproduce the error here. Can you send me your config files? The
>> error might be triggered by certain random numbers, which depend on the PRSS
>> keys. By the way, the error message is about the same every time something
>> goes wrong in a callback. This is because VIFF does not define errbacks. To
>> get a little bit more meaningful output, you can use the --deferred-debug
>> Best regards,
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