Hi,
Most of the EDA and VLSI people are using VIM editor and there is syntax support for Verilog Language. The SystemVerilog is a new language (extension of Verilog and IEEE Compliant) which has more keywords than Verilog and extensions are ".sv" , ".svh" . Now a days most of the VLSI people are working on this new language. Systemverilog.vim is available for download but it is not coming with VIM release. User need to download and make changes in "filetype.vim" file. If VIM support for this new language with the upcoming release, it will be great help full for the people who works with the language Thanks, Vignesh.M Member Technical Staff - VLSI Kacper Technologies (P) Ltd. --~--~---------~--~----~------------~-------~--~----~ You received this message from the "vim_dev" maillist. For more information, visit http://www.vim.org/maillist.php -~----------~----~----~----~------~----~------~--~---
