Hi Bram,
I've made some updates to vhdl.vim. Below is a list of the changes:
- Added new VHDL-2008 types
- Removed non-standard block attributes
- Removed duplicate entries under "type attributes"
- Added new VHDL-2008 attributes
- Overhaul of VHDL operators. Added list of valid operators, and added
linting to check for illegal operators.
- Added FIXME
- Added industry standard (commonly used, but not part of IEEE standard)
preprocessor directives
Best regards,
Daniel
On 25 November 2013 at 08:55, Daniel Kho <[email protected]> wrote:
> Hi Bram,
> Thanks. So, in future, I'll just submit all changes to you. :)
>
> regards, daniel
>
>
>
> On 25 November 2013 06:20, Bram Moolenaar <[email protected]> wrote:
>
>>
>> Daniel -
>>
>> > Hi Bram,
>> > Just would like to check with you, has this patch been applied yet?
>> > Do I do the commit, or I just send over the changes to you and you'll
>> > commit those changes?
>>
>> It has been included, but I only submit changes to runtime files once in
>> a while (running tests takes a bit of time).
>>
>> - Bram
>>
>> --
>> It's totally unfair to suggest - as many have - that engineers are
>> socially
>> inept. Engineers simply have different objectives when it comes to social
>> interaction.
>> (Scott Adams - The Dilbert principle)
>>
>> /// Bram Moolenaar -- [email protected] -- http://www.Moolenaar.net
>> \\\
>> /// sponsor Vim, vote for features -- http://www.Vim.org/sponsor/
>> \\\
>> \\\ an exciting new programming language -- http://www.Zimbu.org
>> ///
>> \\\ help me help AIDS victims -- http://ICCF-Holland.org
>> ///
>>
>
>
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diff -r c8bbd2386d34 runtime/syntax/vhdl.vim
--- a/runtime/syntax/vhdl.vim Wed Oct 07 11:45:06 2015 +0200
+++ b/runtime/syntax/vhdl.vim Mon Oct 12 09:12:49 2015 +0800
@@ -72,6 +72,7 @@
syn keyword vhdlType string severity_level
" Predefined standard ieee VHDL types
syn keyword vhdlType positive natural signed unsigned
+syn keyword vhdlType unresolved_signed unresolved_unsigned u_signed u_unsigned
syn keyword vhdlType line text
syn keyword vhdlType std_logic std_logic_vector
syn keyword vhdlType std_ulogic std_ulogic_vector
@@ -92,12 +93,12 @@
syn match vhdlAttribute "\'right"
syn match vhdlAttribute "\'ascending"
" block attributes
-syn match vhdlAttribute "\'behaviour"
-syn match vhdlAttribute "\'structure"
+"syn match vhdlAttribute "\'behaviour" " Non-standard VHDL
+"syn match vhdlAttribute "\'structure" " Non-standard VHDL
syn match vhdlAttribute "\'simple_name"
syn match vhdlAttribute "\'instance_name"
syn match vhdlAttribute "\'path_name"
-syn match vhdlAttribute "\'foreign"
+syn match vhdlAttribute "\'foreign" " VHPI
" signal attribute
syn match vhdlAttribute "\'active"
syn match vhdlAttribute "\'delayed"
@@ -112,10 +113,9 @@
syn match vhdlAttribute "\'driving_value"
" type attributes
syn match vhdlAttribute "\'base"
-syn match vhdlAttribute "\'high"
-syn match vhdlAttribute "\'left"
+syn match vhdlAttribute "\'subtype"
+syn match vhdlAttribute "\'element"
syn match vhdlAttribute "\'leftof"
-syn match vhdlAttribute "\'low"
syn match vhdlAttribute "\'pos"
syn match vhdlAttribute "\'pred"
syn match vhdlAttribute "\'rightof"
@@ -150,34 +150,76 @@
syn match vhdlNumber "-\=\<\d\+\>"
syn match vhdlNumber "0*2#[01_]\+#\(E[+\-]\=\d\+\)\="
syn match vhdlNumber "0*16#[0-9a-f_]\+#\(E[+\-]\=\d\+\)\="
+
" operators
-syn keyword vhdlOperator and nand or nor xor xnor
-syn keyword vhdlOperator rol ror sla sll sra srl
-syn keyword vhdlOperator mod rem abs not
-syn match vhdlOperator "[&><=:+\-*\/|]"
-syn match vhdlSpecial "[().,;]"
+syn keyword vhdlOperator and nand or nor xor xnor
+syn keyword vhdlOperator rol ror sla sll sra srl
+syn keyword vhdlOperator mod rem abs not
+" TODO remove the following line. You can't have a sequence of */=+ as an
operator for example.
+"syn match vhdlOperator "[&><=:+\-*\/|]"
+" The following lines match valid and invalid operators.
+
+" Concatenation and math operators
+syn match vhdlOperator "&\|+\|-\|\*\|\/"
+
+" Equality and comparison operators
+syn match vhdlOperator "=\|\/=\|>\|<\|>="
+
+" Assignment operators
+syn match vhdlOperator "<=\|:="
+syn match vhdlOperator "=>"
+
+" VHDL-2008 conversion, matching equality/non-equality operators
+syn match vhdlOperator "??\|?=\|?\/=\|?<\|?<=\|?>\|?>="
+
+" Linting for illegal operators
+" '='
+syn match vhdlError "\(=\)[<=&+\-\*\/\\]\+"
+syn match vhdlError "[=&+\-\*\\]\+\(=\)"
+" '>', '<'
+syn match vhdlError "\(>\)[<>&+\-\/\\]\+"
+syn match vhdlError "[>&+\-\/\\]\+\(>\)"
+syn match vhdlError "\(<\)[<&+\-\/\\]\+"
+syn match vhdlError "[<>=&+\-\/\\]\+\(<\)"
+" Covers most operators
+syn match vhdlError
"\(&\|+\|\-\|\*\*\|\/=\|??\|?=\|?\/=\|?<=\|?>=\|>=\|<=\|:=\|=>\)[<>=&+\-\*\\?:]\+"
+syn match vhdlError
"[<>=&+\-\*\\:]\+\(&\|+\|\-\|\*\*\|\/=\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|>=\|<=\|:=\|=>\)"
+syn match vhdlError "\(?<\|?>\)[<>&+\-\*\/\\?:]\+"
+
+"syn match vhdlError
"[?]\+\(&\|+\|\-\|\*\*\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|:=\|=>\)"
+" '/'
+syn match vhdlError "\(\/\)[<>&+\-\*\/\\?:]\+"
+syn match vhdlError "[<>=&+\-\*\/\\:]\+\(\/\)"
+
+syn match vhdlSpecial "<>"
+syn match vhdlSpecial "[().,;]"
+
+
" time
syn match vhdlTime "\<\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>"
syn match vhdlTime
"\<\d\+\.\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>"
+syn case match
syn keyword vhdlTodo contained TODO NOTE
syn keyword vhdlFixme contained FIXME
+syn case ignore
-" Regex for space is '\s'
-" Any number of spaces: \s*
-" At least one space: \s+
-syn region vhdlComment start="/\*" end="\*/" contains=vhdlTodo,vhdlFixme,@Spell
-syn match vhdlComment "--.*" contains=vhdlTodo,vhdlFixme,@Spell
+syn region vhdlComment start="/\*" end="\*/"
contains=vhdlTodo,vhdlFixme,@Spell
+syn match vhdlComment "\(^\|\s\)--.*"
contains=vhdlTodo,vhdlFixme,@Spell
+
+" Industry-standard directives. These are not standard VHDL, but are commonly
+" used in the industry.
syn match vhdlPreProc "/\* synthesis .* \*/"
+"syn match vhdlPreProc "/\* simulation .* \*/"
syn match vhdlPreProc "/\* pragma .* \*/"
syn match vhdlPreProc "/\* synopsys .* \*/"
syn match vhdlPreProc "--\s*synthesis .*"
+"syn match vhdlPreProc "--\s*simulation .*"
syn match vhdlPreProc "--\s*pragma .*"
syn match vhdlPreProc "--\s*synopsys .*"
-" syn match vhdlGlobal "[\'$#~!%@?\^\[\]{}\\]"
"Modify the following as needed. The trade-off is performance versus
functionality.
-syn sync minlines=200
+syn sync minlines=600
" Define the default highlighting.
" For version 5.7 and earlier: only when not done already
@@ -203,7 +245,7 @@
HiLink vhdlTime Number
HiLink vhdlType Type
HiLink vhdlOperator Operator
-" HiLink vhdlGlobal Error
+ HiLink vhdlError Error
HiLink vhdlAttribute Special
HiLink vhdlPreProc PreProc
