Hi
Is it possible to make the = command file type dependend.
For example if the file is called my_design.vhd the filteype is then VHDL
End then the = command should 'clean up' the code into the VHDL style below
So
- after the word begin an indent should occur on the next line
- the same applies for the word if, while and for
- if ends with 'end if';
- case ends with 'end case'
- a process is a kind of a loop that and with end process
- the same applies for entity, architecture
- for end with 'end loop'
- same applies for while
Some VHDL examples:
process()
begin
if rising_edge(clk) then
...
elsif
...
end if;
end procss
entity AAA is
port
(
CLK: in std_logic;
COUNT: out integer
);
end AAA;
architecture behave of AAA is
begin
E <= F;
end AAA;
while condition loop
A <= B;
D <= C;
end loop;
for identifier in range loop
AA <= BB;
CC <= DD;
end loop;
case HHH is
when RRR =>
if X='0' then
...
elsif X='1' then
...
end if;
when others =>
null;
end case;
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