On 13 Aug 2010, at 08:04, Jeri Raye wrote: >> entity is a VHDL word, as well as if. >> foo is a made up word. >> > > It's also for the VHDL reserved words process, case, architecture. > I can't believe VIM can't fold reserved words? > Or is this a bug? > > I did change entity into entit (so removing the y char) in the given syn > region. > When I now type entit in my VHDL file the word is not higlighted as a > VHDL word and the folding goes ok. > Why doesn't it work for real VHDL words? > Are they declared as 'syntax keyword'? If so, I think that trumps any attempt to redefine them as regions/matches/etc. I had that problem when writing a syntax file for another language; declaring keywords highlights them unconditionally, irrespective of context, and prevents their use in higher level semantic contexts. In the end I got rid of all keywords and declared everything with syntax match' and 'syntax region'.
Regards, Andy -- Andrew Long andrew dot long at mac dot com
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