Larry Gray wrote:
for example, a section of verilog code:
// define input and output ports
input A;
output B;
// main logic
wire C;
assign C = A & B;
A,B and C are all treated as variables, so displayed in the same color. I'm
wondering if vim can use different color for A and B than C?
syn keyword User1 A B
syn keyword User2 C
and define User1 and User2 to whatever you want.
Now, that said: I suspect that what you want is for vim to be a verilog
interpreter; to dynamically determine that A, B, and C are input,
output, and assign style variables. Vim is not a verilog interpreter,
so it doesn't have a clue that A, B, and C are whatever types that
verilog might have.
Regards,
C Campbell
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