在 2021/8/16 下午7:48, Michael S. Tsirkin 写道:
On Mon, Aug 16, 2021 at 12:05:50PM +0530, Srivatsa Vaddagiri wrote:
* Michael S. Tsirkin <[email protected]> [2021-08-16 01:35:46]:
So thinking about all this, quite early in the setup process we
have:
/* Figure out what features the device supports. */
device_features = dev->config->get_features(dev);
isn't this sufficient? this will flush out
all writes and device can defer responding to reads
until reset is complete.
Hmm not sure if that's possible in all MMIO devices? I think a while back Jason
felt some of the MMIO devices, their registers could act as plain DRAM for
reads, which means device can't block such reads?
- vatsa
Is it worth bothering about theoretical issues though? Jason what is
your take?
Re-read the spec, and it said
"
MMIO Device Register Layout
"
I believe plain DRAM will not behave like a register. So we don't need
to worry about that.
But they are indeed devices that act as a plain DRAM for their control
path, which might requires new transports[1].
Another question is that what makes PCI differ from MMIO. (E.g PCI
requires a re-read but MMIO doesn't)
[1] https://lkml.org/lkml/2020/9/1/255
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