On 03/21/2013 09:11 AM, Michael S. Tsirkin wrote:
>>
>> It is really, really, nasty, not to mention slow.
>
> Almost everything we do is through DMA, except a single write
> to start transmit and a single read to clear interrupts. So all it means
> is we do 2 io writes or reads per packet instead of 1. Seems harmless
> enough. A bit slower than native but should be good enough for
> BIOS. Needs no resources at all. Why nasty? What's not to like?
>
Corner cases galore... including the statefulness and non-atomicity of
config space writes (MMCONFIG is obviously not an option here.) It
requires a minimum of four operations to do it safely.
>
> Thanks. Same place in latest 3.0:
> A PCI Express Endpoint must not depend on operating system allocation of
> I/O resources claimed through BAR(s).
> A PCI Express Endpoint must not generate I/O Requests.
> of course this only applies to express :)
>
And it does... but it has implications for the OS resource manager that
if Linux violates, we need to fix it. We should not fail a device in
generic code because an I/O BAR allocation fails. The device driver may
opt to fail the allocation.
(Note that having an I/O BAR is not *generating* an I/O request.)
-hpa
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