On Wed, Jun 23, 2021 at 08:40:00AM +0200, Joerg Roedel wrote:
> From: Brijesh Singh <[email protected]>
> 
> Add the necessary defines for supporting the GHCB version 2 protocol.
> This includes defines for:
> 
>       - MSR-based AP hlt request/response
>       - Hypervisor Feature request/response
> 
> This is the bare minimum of requests that need to be supported by a GHCB
> version 2 implementation. There are more requests in the specification,
> but those depend on Secure Nested Paging support being available.
> 
> These defines are shared between SEV host and guest support, so they are
> submitted as an individual patch without users yet to avoid merge
> conflicts in the future.
> 
> Signed-off-by: Brijesh Singh <[email protected]>
> Signed-off-by: Tom Lendacky <[email protected]>
> Co-developed-by: Tom Lendacky <[email protected]>
> Signed-off-by: Joerg Roedel <[email protected]>
> ---
>  arch/x86/include/asm/sev-common.h | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/arch/x86/include/asm/sev-common.h 
> b/arch/x86/include/asm/sev-common.h
> index 1cc9e7dd8107..9aa2f29b4c97 100644
> --- a/arch/x86/include/asm/sev-common.h
> +++ b/arch/x86/include/asm/sev-common.h
> @@ -47,6 +47,21 @@
>               (((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << 
> GHCB_MSR_CPUID_REG_POS) | \
>               (((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS))
>  
> +/* AP Reset Hold */
> +#define GHCB_MSR_AP_RESET_HOLD_REQ           0x006
> +#define GHCB_MSR_AP_RESET_HOLD_RESP          0x007
> +#define GHCB_MSR_AP_RESET_HOLD_RESULT_POS    12
> +#define GHCB_MSR_AP_RESET_HOLD_RESULT_MASK   GENMASK_ULL(51, 0)
> +
> +/* GHCB Hypervisor Feature Request/Response */
> +#define GHCB_MSR_HV_FT_REQ                   0x080
> +#define GHCB_MSR_HV_FT_RESP                  0x081
> +#define GHCB_MSR_HV_FT_POS                   12
> +#define GHCB_MSR_HV_FT_MASK                  GENMASK_ULL(51, 0)
> +
> +#define GHCB_MSR_HV_FT_RESP_VAL(v)           \
> +     ((unsigned long)((v) >> GHCB_MSR_HV_FT_POS) & GHCB_MSR_HV_FT_MASK)
> +

Ok, so I took a critical look at this and it doesn't make sense to have
a differently named define each time you need the [63:12] slice of
GHCBData. So you can simply use GHCB_DATA(msr_value) instead, see below.

Complaints?

---
From: Brijesh Singh <[email protected]>
Date: Wed, 23 Jun 2021 08:40:00 +0200
Subject: [PATCH] x86/sev: Add defines for GHCB version 2 MSR protocol requests

Add the necessary defines for supporting the GHCB version 2 protocol.
This includes defines for:

        - MSR-based AP hlt request/response
        - Hypervisor Feature request/response

This is the bare minimum of requests that need to be supported by a GHCB
version 2 implementation. There are more requests in the specification,
but those depend on Secure Nested Paging support being available.

These defines are shared between SEV host and guest support.

  [ bp: Fold in 
https://lkml.kernel.org/r/[email protected] too.
        Simplify the brewing macro maze into readability. ]

Co-developed-by: Tom Lendacky <[email protected]>
Signed-off-by: Tom Lendacky <[email protected]>
Signed-off-by: Brijesh Singh <[email protected]>
Signed-off-by: Joerg Roedel <[email protected]>
Signed-off-by: Borislav Petkov <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
---
 arch/x86/include/asm/sev-common.h | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/sev-common.h 
b/arch/x86/include/asm/sev-common.h
index 629c3df243f0..2cef6c5a52c2 100644
--- a/arch/x86/include/asm/sev-common.h
+++ b/arch/x86/include/asm/sev-common.h
@@ -9,8 +9,13 @@
 #define __ASM_X86_SEV_COMMON_H
 
 #define GHCB_MSR_INFO_POS              0
-#define GHCB_MSR_INFO_MASK             (BIT_ULL(12) - 1)
+#define GHCB_DATA_LOW                  12
+#define GHCB_MSR_INFO_MASK             (BIT_ULL(GHCB_DATA_LOW) - 1)
 
+#define GHCB_DATA(v)                   \
+       (((unsigned long)(v) & ~GHCB_MSR_INFO_MASK) >> GHCB_DATA_LOW)
+
+/* SEV Information Request/Response */
 #define GHCB_MSR_SEV_INFO_RESP         0x001
 #define GHCB_MSR_SEV_INFO_REQ          0x002
 #define GHCB_MSR_VER_MAX_POS           48
@@ -28,6 +33,7 @@
 #define GHCB_MSR_PROTO_MAX(v)          (((v) >> GHCB_MSR_VER_MAX_POS) & 
GHCB_MSR_VER_MAX_MASK)
 #define GHCB_MSR_PROTO_MIN(v)          (((v) >> GHCB_MSR_VER_MIN_POS) & 
GHCB_MSR_VER_MIN_MASK)
 
+/* CPUID Request/Response */
 #define GHCB_MSR_CPUID_REQ             0x004
 #define GHCB_MSR_CPUID_RESP            0x005
 #define GHCB_MSR_CPUID_FUNC_POS                32
@@ -45,6 +51,14 @@
                (((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << 
GHCB_MSR_CPUID_REG_POS) | \
                (((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS))
 
+/* AP Reset Hold */
+#define GHCB_MSR_AP_RESET_HOLD_REQ             0x006
+#define GHCB_MSR_AP_RESET_HOLD_RESP            0x007
+
+/* GHCB Hypervisor Feature Request/Response */
+#define GHCB_MSR_HV_FT_REQ                     0x080
+#define GHCB_MSR_HV_FT_RESP                    0x081
+
 #define GHCB_MSR_TERM_REQ              0x100
 #define GHCB_MSR_TERM_REASON_SET_POS   12
 #define GHCB_MSR_TERM_REASON_SET_MASK  0xf
-- 
2.29.2

-- 
Regards/Gruss,
    Boris.

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