Define the HFI device commands and properties needed to discover DCP capabilities and register display resources. The KMS backend cannot size or allocate the firmware-owned pipeline without these protocol definitions.
Describe device commands, resource data, and capability property identifiers used by the DCP device and KMS layers. Assisted-by: LLM Signed-off-by: Jayant Shekhar <[email protected]> --- drivers/gpu/drm/msm/dcp/hfi/hfi_commands_device.h | 78 ++++++++++++++++ drivers/gpu/drm/msm/dcp/hfi/hfi_defs_device.h | 61 ++++++++++++ .../gpu/drm/msm/dcp/hfi/hfi_properties_device.h | 102 +++++++++++++++++++++ 3 files changed, 241 insertions(+) diff --git a/drivers/gpu/drm/msm/dcp/hfi/hfi_commands_device.h b/drivers/gpu/drm/msm/dcp/hfi/hfi_commands_device.h new file mode 100644 index 000000000000..abf15e6ceaec --- /dev/null +++ b/drivers/gpu/drm/msm/dcp/hfi/hfi_commands_device.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __H_HFI_COMMANDS_DEVICE_H__ +#define __H_HFI_COMMANDS_DEVICE_H__ + +/* Device-level command range. */ +#define HFI_COMMAND_DEVICE_BEGIN 0x01000000 + +/* Initialize the device and return firmware capabilities. */ +#define HFI_COMMAND_DEVICE_INIT 0x01000001 + +/* Device, display, and pipeline capability response. */ +#define HFI_COMMAND_DEVICE_INIT_DEVICE_CAPS 0x01000002 + +/* VIG pipeline capability response. */ +#define HFI_COMMAND_DEVICE_INIT_VIG_CAPS 0x01000003 + +/* DMA pipeline capability response. */ +#define HFI_COMMAND_DEVICE_INIT_DMA_CAPS 0x01000004 + +/* Common VIG/DMA capability response. */ +#define HFI_COMMAND_DEVICE_INIT_COMMON_LAYER_CAPS 0x01000005 + +/* Display capability response. */ +#define HFI_COMMAND_DEVICE_INIT_DISPLAY_CAPS 0x01000006 + +/* Writeback capability response. */ +#define HFI_COMMAND_DEVICE_INIT_DISPLAY_WB_CAPS 0x01000007 + +/* Register clocks and bandwidth resources with firmware. */ +#define HFI_COMMAND_DEVICE_RESOURCE_REGISTER 0x01000008 + +/* Firmware requests a resource vote from the host. */ +#define HFI_COMMAND_DEVICE_CALLBACK_RESOURCE_VOTE 0x01000009 + +/* VIG rect-1 capability response. */ +#define HFI_COMMAND_DEVICE_INIT_VIG_R1_CAPS 0x0100000a + +/* DMA rect-1 capability response. */ +#define HFI_COMMAND_DEVICE_INIT_DMA_R1_CAPS 0x0100000b + +/* Provide the last-command buffer to firmware. */ +#define HFI_COMMAND_DEVICE_LUT_DMA_LAST_CMD 0x0100000c + +/* Deinitialize the device. */ +#define HFI_COMMAND_DEVICE_DEINIT 0x0100000d + +/* LSR writeback CSC layer capability response. */ +#define HFI_COMMAND_DEVICE_INIT_LSR_WB_CSC_LAYER_CAPS 0x0100000e + +/* LSR writeback reprojection layer capability response. */ +#define HFI_COMMAND_DEVICE_INIT_LSR_WB_REPROJ_LAYER_CAPS 0x0100000f + +/* LSR writeback CSC output capability response. */ +#define HFI_COMMAND_DEVICE_INIT_DISPLAY_LSR_WB_CSC_CAPS 0x01000010 + +/* LSR writeback reprojection output capability response. */ +#define HFI_COMMAND_DEVICE_INIT_DISPLAY_LSR_WB_REPROJ_CAPS 0x01000011 + +/* Configure the hardware-fence HFI queue. */ +#define HFI_COMMAND_DEVICE_HWFENCE_HFI_CONFIG 0x01000012 + +/* Update hotplug state and provide EDID/mode buffers. */ +#define HFI_COMMAND_DEVICE_HOT_PLUG_DETECT 0x01000013 + +/* Configure resources shared across virtual machines. */ +#define HFI_COMMAND_DEVICE_RESOURCE_CTRL 0x01000014 + +/* Notify firmware of a subsystem restart. */ +#define HFI_COMMAND_DEVICE_SUBSYSTEM_RESTART_NOTIFY 0x01000015 + +/* End of device-level command range. */ +#define HFI_COMMAND_DEVICE_END 0x01ffffff + +#endif /* __H_HFI_COMMANDS_DEVICE_H__ */ diff --git a/drivers/gpu/drm/msm/dcp/hfi/hfi_defs_device.h b/drivers/gpu/drm/msm/dcp/hfi/hfi_defs_device.h new file mode 100644 index 000000000000..c6c8fb556c3e --- /dev/null +++ b/drivers/gpu/drm/msm/dcp/hfi/hfi_defs_device.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __H_HFI_DEFS_DEVICE_H__ +#define __H_HFI_DEFS_DEVICE_H__ + +#include "hfi_defs_common.h" + +/* Hotplug state for dynamic display interfaces. */ +struct hfi_device_hotplug_config { + u32 orientation; + u32 port_index; + u32 pin_config; + u32 hpd_state; + u32 hpd_irq; +}; + +/* Display resource ownership state. */ +enum hfi_device_res_state { + HFI_DEVICE_RESOURCE_ACQUIRE = 0x0, + HFI_DEVICE_RESOURCE_RELEASE = 0x1, + HFI_DEVICE_RESOURCE_SHARED = 0x2, + HFI_DEVICE_RESOURCE_PRE_RELEASE = 0x3, +}; + +/* Virtualized display-resource types. */ +enum hfi_device_resource_type { + HFI_DEVICE_RESOURCE_DISPLAY, +}; + +/* Virtualized display-resource configuration. */ +struct hfi_device_resource_config { + u32 disp_mask; + enum hfi_device_res_state vm_state; + u32 resource_type; + u32 reserved[2]; +}; + +/* Subsystem-restart event. */ +enum hfi_device_ssr_event { + HFI_DEVICE_SSR_EVENT_START = 0, + HFI_DEVICE_SSR_EVENT_END = 1, +}; + +/* Subsystem-restart information. */ +struct hfi_device_ssr_info { + enum hfi_subsystem_type subsystem_type; + enum hfi_device_ssr_event ssr_event; + u32 reserved1; + u32 reserved2; +}; + +/* Active layer mask for a display. */ +struct hfi_device_active_layers_info { + u32 display_id; + u32 layers_mask; +}; + +#endif /* __H_HFI_DEFS_DEVICE_H__ */ diff --git a/drivers/gpu/drm/msm/dcp/hfi/hfi_properties_device.h b/drivers/gpu/drm/msm/dcp/hfi/hfi_properties_device.h new file mode 100644 index 000000000000..790fcca6ac0a --- /dev/null +++ b/drivers/gpu/drm/msm/dcp/hfi/hfi_properties_device.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __H_HFI_PROPERTIES_DEVICE_H__ +#define __H_HFI_PROPERTIES_DEVICE_H__ + +/* Device-property range. */ +#define HFI_PROPERTY_DEVICE_BEGIN 0x00010000 + +/* DCP hardware version. */ +#define HFI_PROPERTY_DEVICE_INIT_DCP_HW_VERSION 0x00010001 + +/* MDSS hardware version. */ +#define HFI_PROPERTY_DEVICE_INIT_MDSS_HW_VERSION 0x00010002 + +/* VIG layer indices; the high byte identifies the rectangle. */ +#define HFI_PROPERTY_DEVICE_INIT_VIG_INDICES 0x00010004 + +/* DMA layer indices; the high byte identifies the rectangle. */ +#define HFI_PROPERTY_DEVICE_INIT_DMA_INDICES 0x00010005 + +/* DCP firmware version. */ +#define HFI_PROPERTY_DEVICE_INIT_DCP_FW_VERSION 0x00010003 + +/* Maximum display count. */ +#define HFI_PROPERTY_DEVICE_INIT_MAX_DISPLAY_COUNT 0x00010006 + +/* Writeback block indices. */ +#define HFI_PROPERTY_DEVICE_INIT_WB_INDICES 0x00010007 + +/* Maximum linear writeback size: width [31:16], height [15:0]. */ +#define HFI_PROPERTY_DEVICE_INIT_MAX_WB_LINEAR_RESOLUTION 0x00010008 + +/* Maximum UBWC writeback size: width [31:16], height [15:0]. */ +#define HFI_PROPERTY_DEVICE_INIT_MAX_WB_UBWC_RESOLUTION 0x00010009 + +/* DSI interface indices. */ +#define HFI_PROPERTY_DEVICE_INIT_DSI_INDICES 0x0001000a + +/* Maximum DSI size: width [31:16], height [15:0]. */ +#define HFI_PROPERTY_DEVICE_INIT_MAX_DSI_RESOLUTION 0x0001000b + +/* DisplayPort interface indices. */ +#define HFI_PROPERTY_DEVICE_INIT_DP_INDICES 0x0001000c + +/* Maximum DisplayPort size: width [31:16], height [15:0]. */ +#define HFI_PROPERTY_DEVICE_INIT_MAX_DP_RESOLUTION 0x0001000d + +/* Downscaler indices. */ +#define HFI_PROPERTY_DEVICE_INIT_DS_INDICES 0x0001000e + +/* Maximum downscaler size: width [31:16], height [15:0]. */ +#define HFI_PROPERTY_DEVICE_INIT_MAX_DS_RESOLUTION 0x0001000f + +/* Core average-bandwidth vote. */ +#define HFI_PROPERTY_DEVICE_CORE_AB 0x00010010 + +/* Core instantaneous-bandwidth vote. */ +#define HFI_PROPERTY_DEVICE_CORE_IB 0x00010011 + +/* Core power-rail vote. */ +#define HFI_PROPERTY_DEVICE_CORE_POWER_RAIL 0x00010012 + +/* LLCC average-bandwidth vote. */ +#define HFI_PROPERTY_DEVICE_LLCC_AB 0x00010013 + +/* LLCC instantaneous-bandwidth vote. */ +#define HFI_PROPERTY_DEVICE_LLCC_IB 0x00010014 + +/* DRAM average-bandwidth vote. */ +#define HFI_PROPERTY_DEVICE_DRAM_AB 0x00010015 + +/* DRAM instantaneous-bandwidth vote. */ +#define HFI_PROPERTY_DEVICE_DRAM_IB 0x00010016 + +/* LSR writeback CSC indices. */ +#define HFI_PROPERTY_DEVICE_INIT_LSR_WB_CSC_INDICES 0x00010017 + +/* LSR writeback reprojection indices. */ +#define HFI_PROPERTY_DEVICE_INIT_LSR_WB_REPROJ_INDICES 0x00010018 + +/* LSR writeback CSC layer indices. */ +#define HFI_PROPERTY_DEVICE_INIT_LSR_WB_CSC_LAYER_INDICES 0x00010019 + +/* LSR writeback reprojection layer indices. */ +#define HFI_PROPERTY_DEVICE_INIT_LSR_WB_REPROJ_LAYER_INDICES 0x0001001a + +/* System-cache staling configuration. */ +#define HFI_PROPERTY_DEVICE_INIT_SYS_CACHE_STALING 0x0001001b + +/* Active layers per display. */ +#define HFI_PROPERTY_DEVICE_INIT_ACTIVE_LAYERS 0x0001001c + +/* Writeback DNSC support indices. */ +#define HFI_PROPERTY_DEVICE_INIT_WB_DNSC_SUPPORT_INDICES 0x0001001d + +/* End of device-property range. */ +#define HFI_PROPERTY_DEVICE_END 0x0001ffff + +#endif /* __H_HFI_PROPERTIES_DEVICE_H__ */ -- 2.43.0
